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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00368 rev. *j revised april 21, 2017 S25FS128S s25fs256s 1.8 v, serial peripheral interface with multi-i/o, mirrorbit ? non-volatile flash features ? density ? S25FS128S-128 mbits (16 mbytes) ? s25fs256s-256 mbits (32 mbytes) ? serial peripheral interface (spi) ? spi clock polarity and phase modes 0 and 3 ? double data rate (ddr) option ? extended addressing: 24- or 32-bit address options ? serial command subset and footprint compatible with s25fl-a, s25fl-k, s25fl-p, and s25fl-s spi families ? multi i/o command subset and footprint compatible with s25fl-p, and s25fl-s spi families ? read ? commands: normal, fast, d ual i/o, quad i/o, ddr quad i/o ? modes: burst wrap, continuous (xip), qpi ? serial flash discoverable parameters (sfdp) and common flash interface (c fi), for configuration information ? program ? 256- or 512-byte page programming buffer ? program suspend and resume ? automatic ecc ? internal hardware error correction code generation with single-bit error correction ? erase ? hybrid sector option ? physical set of eight 4-kbyt e sectors and one 32-kbyte sector at the top or bottom of address space with all remaining sector s of 64 kbytes ? uniform sector option ? uniform 64-kbyte or 256- kbyte blocks for software compatibility with higher density and future devices ? erase suspend and resume ? erase status evaluation ? 100,000 program-erase cycles, minimum ? 20 year data retention, minimum ? security features ? one-time program (otp) array of 1024 bytes ? block protection: ? status register bits to control protection against program or erase of a contiguous range of sectors ? hardware and software control options ? advanced sector protection (asp) ? individual sector protection controlled by boot code or password ? option for password control of read access ? technology ? cypress 65 nm mirrorbit ? technology with eclipse ? architecture ? supply voltage ? 1.7v to 2.0v ? temperature range / grade ? industrial (-40c to +85c) ? industrial plus (?40c to +105c) ? automotive aec-q100 grade 3 (?40c to +85c) ? automotive aec-q100 grade 2 (?40c to +105c) ? automotive aec-q100 grade 1 (?40c to +125c) ? packages (all pb-free) ? 8-lead soic 208 mil (soc008) ? fs128s only ?wson 6 ? 5 mm (wnd008) ? fs128s only ?wson 6 ? 8 mm (wnh008) ? 16-lead soic 300 mil (so3016 ? fs256s only) ? bga-24 6 ? 8 mm ?5 ? 5 ball (fab024) footprint ?4 ? 6 ball (fac024) footprint ? known good die, and known tested die
document number: 002-00368 rev. *j page 2 of 151 S25FS128S s25fs256s performance summary maximum read rates command clock rate (mhz) mbytes/s read 50 6.25 fast read 133 16.5 dual read 133 33 quad read 133 66 maximum read rates ddr command clock rate (mhz) mbytes/s ddr quad i/o read 80 80 typical program and erase rates operation kbytes/s page programming (256-bytes page buffer) 712 page programming (512-bytes page buffer) 1080 4-kbyte physical sector eras e (hybrid sector option) 16 64-kbyte physical sector erase (hybrid sector option) 275 256-kbyte sector erase (uniform logical sector option) 275 typical current consumption (?40c to +85c) operation current (ma) serial read 50 mhz 10 serial read 133 mhz 20 quad read 133 mhz 60 quad ddr read 80 mhz 70 program 60 erase 60 standby 0.025 deep power-down 0.006
document number: 002-00368 rev. *j page 3 of 151 S25FS128S s25fs256s contents performance summary ........................................................ 2 1. overview ....................................................................... 4 1.1 general description ....................................................... 4 1.2 migration notes.............................................................. 5 1.3 glossary......................................................................... 7 1.4 other resources............................................................ 8 2. signal descriptions ..................................................... 9 2.1 input/output summary................................................... 9 2.2 multiple input / output (mio) ........... ........... ........... ....... 10 2.3 serial clock (sck) ....................................................... 10 2.4 chip select (cs#) ........................................................ 10 2.5 serial input (si) / io0 ................................................... 10 2.6 serial output (so) / io1............................................... 10 2.7 write protect (wp#) / io2 ............................................ 10 2.8 io3 / reset# . .............. .............. .............. ........... ....... 11 2.9 voltage supply (vcc).................................................. 11 2.10 supply and signal ground (v ss ) ................................. 11 2.11 not connected (nc) .................................................... 11 2.12 reserved for future use (rfu )................................... 11 2.13 do not use (dnu) ................. .............. .............. .......... 12 2.14 block diagrams............................................................ 12 3. signal protocols ......................................................... 13 3.1 spi clock modes ......................................................... 13 3.2 command protocol ...................................................... 14 3.3 interface states............................................................ 18 3.4 configuration register effects on the interface ........... 21 3.5 data protection ............................................................ 21 4. electrical specifications ............................................ 22 4.1 absolute maximum ratings ...... ................................... 22 4.2 thermal resistance ..................................................... 22 4.3 latch-up characteristics.............................................. 23 4.4 operating ranges........................................................ 23 4.5 power-up and power-down ..... ................................... 24 4.6 dc characteristics ....................................................... 26 5. timing specifications ................................................ 27 5.1 key to switching waveforms . ...................................... 27 5.2 ac test conditions ...................................................... 27 5.3 reset............................................................................ 28 5.4 sdr ac characteristics............................................... 30 5.5 ddr ac characteristics .............................................. 32 6. physical interface ...................................................... 35 6.1 soic 16-lead package ............................................... 35 6.2 8-connector packages .......... .............. .............. .......... 37 6.3 fab024 24-ball bga package .................................... 41 6.4 fac024 24-ball bga package .................................... 43 7. address space maps ................................................. 45 7.1 overview ...................................................................... 45 7.2 flash memory array..................................................... 45 7.3 id-cfi address space ................................................. 48 7.4 jedec jesd216 serial flash discoverable parameters (sfdp) space.............................................................. 48 7.5 otp address space ..................................................... 49 7.6 registers....................................................................... 50 8. data protection ........................................................... 67 8.1 secure silicon region (otp). .......... ........... ........... ....... 67 8.2 write enable command.......... ............... .............. ......... 68 8.3 block protection ............................................................ 68 8.4 advanced sector protection ......................................... 69 8.5 recommended protection process .............................. 74 9. commands .................................................................. 76 9.1 command set summary............................................... 78 9.2 identification commands .............................................. 82 9.3 register access commands......................................... 85 9.4 read memory array commands ............. .............. ....... 95 9.5 program flash array command s ............................... 103 9.6 erase flash array commands .................................... 105 9.7 one-time program array commands ........................ 111 9.8 advanced sector protection commands .................... 112 9.9 reset commands ....................................................... 118 9.10 dpd commands ......................................................... 120 10. embedded algorith m performance tables ............ 122 11. data integrity ............................................................. 123 11.1 erase endurance ........................................................ 123 11.2 data retention ..... ....................................................... 123 11.3 serial flash discoverable parameters (sfdp) address map............................................................................. 123 11.4 device id and common flash interface (id-cfi) address map............................................................................. 126 11.5 initial delivery state ........... ......................................... 143 12. ordering part number .............................................. 144 13. contact ....................................................................... 146 14. revision history ........................................................ 147
document number: 002-00368 rev. *j page 4 of 151 S25FS128S s25fs256s 1. overview 1.1 general description the cypress s25fs-s family devices are fl ash non-volatile memory products using: ? mirrorbit technology - that stores two data bits in each memory array transistor ? eclipse architecture - that dramatically improves program and erase performance ? 65 nm process lithography thes25fs-s family connects to a host system via a serial periphera l interface (spi). tr aditional spi single bit serial input an d output (single i/o or sio) is supported as well as optional 2-bit (dual i/o or dio) and 4-bit wide qu ad i/o (qio) or quad perip heral interface (qpi) serial commands. this multip le width interface is called spi multi-i/o or mio. in addition, there are double da ta rate (ddr) read commands for qio and qpi that transfer address and read data on both edges of the clock. the fs-s eclipse architecture features a page programming buffer that allows up to 512 bytes to be programmed in one operation, resulting in faster effective programming and erase than prior generation spi progr am or erase algorithms. executing code directly from flash memory is often called execute- in-place or xip. by using s25f s-s family devices at the highe r clock rates supported, with quad or ddr q uad commands, the instruction read transfer rate can match or exceed traditional paral lel interface, asynchronous, nor flash memories, while reducing signal count dramatically. the s25fs-s family products offer high de nsities coupled with the flexibility and fast performance required by a variety of mob ile or embedded applications. they are an excellent solution for system s with limited space, signal connecti ons, and power. they are i deal for code shadowing to ram, executing code dire ctly (xip), and storing reprogrammable data.
document number: 002-00368 rev. *j page 5 of 151 S25FS128S s25fs256s 1.2 migration notes 1.2.1 features comparison the s25fs-s family is command subset and footprint compatible with prior generation fl-s, fl-k, and fl-p families. however, the power supply and interface voltages are nominal 1.8 v. notes: 1. the 256b program page option only for 128-mb and 256-mb density fl-s devices. 2. the fl-p column indicates fl129p mio spi device (for 128-mb density), fl128p does not support mio, otp, or 4-kb sectors. 3. 64-kb sector erase option only for 128-mb/256-mb density fl-p, fl-s and fs-s devices. 4. the fl-k family devices can erase 4-kb sectors in groups of 32 kb or 64 kb. 5. 512-mb/1-gb fl-s devices support 256-kb sector only. 6. only 128-mb/256-mb density fl-s devices have 4-kb parameter sector option. 7. refer to individual data sheets for further details. 1.2.2 known differences from prior generations 1.2.2.1 error reporting fl-k and fl-p memories either do not have error status bits or do not set them if program or er ase is attempte d on a protected sector. the fs-s and fl-s families do have error reporting stat us bits for program and erase operations. these can be set when there is an internal failure to program or erase, or when there is an attempt to progr am or erase a protected sector. in these cases the program or erase operation did not complete as requested by the command. the p_err or e_err bits and the wip bit will be cypress spi families comparison parameter fs-s fl-s fl-k fl-p technology node 65 nm 65 nm 90 nm 90 nm architecture mirrorbit eclipse mirrorbit eclipse floating gate mirrorbit density 128 mb, 256 mb 128 mb, 256 mb, 512 mb, 1 gb 4 mb - 128 mb 32 mb - 256 mb bus width x1, x2, x4 x1, x2, x4 x1, x2, x4 x1, x2, x4 supply voltage 1.7 v?2.0 v 2.7 v?3.6 v / 1.65 v?3.6 v v io 2.7 v?3.6 v 2.7 v?3.6 v normal read speed (sdr) 6 mb/s (50 mhz) 6 mb/s (50 mhz) 6 mb/s (50 mhz) 6 mb/s (40 mhz) fast read speed (sdr) 16.5 mb/s (133 mhz) 17 mb/s (133 mhz) 13 mb/s (104 mhz) 13 mb/s (104 mhz) dual read speed (sdr) 33 mb/s (133 mhz) 26 mb/s (104 mhz) 26 mb/s (104 mhz) 20 mb/s (80 mhz) quad read speed (sdr) 66 mb/s (133 mhz) 52 mb/s (104 mhz) 52 mb/s (104 mhz) 40 mb/s (80 mhz) quad read speed (ddr) 80 mb/s (80 mhz) 80 mb/s (80 mhz) program buffer size 256b / 512b 256b / 512b 256b 256b erase sector size 64 kb / 256 kb 64 kb / 256 kb 4 kb / 32 kb / 64 kb 64 kb / 256 kb parameter sector size 4 kb (option) 4 kb (option) 4 kb 4 kb sector erase rate (typ.) 500 kb/s 500 kb/s 136 kb/s (4 kb) 437 kb/s (64 kb) 130 kb/s page programming rate (typ.) 0.71 mb/s (256b) 1.08 mb/s (512b) 1.2 mb/s (256b) 1.5 mb/s (512b) 365 kb/s 170 kb/s otp 1024b 1024b 768b (3x256b) 506b advanced sector protection yes yes no no auto boot mode no yes no no erase suspend/resume yes yes yes no program suspend/resume yes yes yes no deep power-down yes no yes yes operating temperature ?40 c to +85 c / +105 c / +125 c ?40 c to +85 c / +105 c ?40 c to +85 c ?40 c to +85 c / +105 c
document number: 002-00368 rev. *j page 6 of 151 S25FS128S s25fs256s set to and remain 1 in sr1v. the clear status register command must be sent to clear the errors and return the device to standby state. 1.2.2.2 secure silicon region (otp) the fs-s size and format (address map) of the one-time program area is different from fl-k and fl-p generations. the method for protecting each portion of the otp area is different. for additional details see secure silicon region (otp) on page 67 . 1.2.2.3 configuration register freeze bit the configuration regi ster 1 freeze bit cr1v[0], locks th e state of the block protection bits (sr1nv[4:2] and sr1v[4:2]), tbparm_o bit (cr1nv[2]), and tbprot_o bit (c r1nv[5]), as in prior generations. in th e fs-s and fl-s fam ilies the freeze bit also locks the state of the configuratio n register 1 bpnv_o bit (cr1nv[3]), and the secure silicon region (otp) area. 1.2.2.4 sector erase commands the command for erasing a 4-kbyte sector is supported only for us e on 4-kbyte parameter sectors at the top or bottom of the fs- s device address space. the command for erasing an 8-kbyte area (t wo 4-kbyte sectors) is not supported. the command for erasing a 32-kbyte area (eig ht 4-kbyte sectors) is not supported. the sector erase command (se) for fs-s 64- kbyte sectors is supported when the confi guration option for uniform 64-kbyte sector is selected or, when the hybrid configuration opt ion for 4-kbyte parameter sect ors with 64-kbyte uniform sectors is used. when the hybrid option is in use, the 64-kbyte eras e command may be used to erase the 32-kbyte of address space adjacent to the group of eight 4-kbyte sectors. the 64-kbyt e erase command in this case is erasing the 64-kb yte sector that is partially overlaid by the group of eight 4-kbyte sectors without affecting the 4-kbyte sectors. this provides erase cont rol over the 32 kbytes of address space without also forcing the erase of the 4-kb yte sectors. this is different behavior t han implemented in the fl-s family. in the f l-s family, the 64-kbyte sector erase command can be applied to a 64- kbyte block of 4-kbyte sectors to erase the entire block of parameter sectors in a single operation. in the fs-s, the paramet er sectors do not fill an entire 64-kbyte block so only the 4- kbyte parameter sector erase (20h) is used to erase parameter sectors. the erase command for a 256-kbyte sector replaces the 64-k byte erase command when the conf iguration option for 256-kbyte uniform logical sectors is used. 1.2.2.5 deep power-down the deep power-down (dpd) function is sup ported in the fs-s family of devices. 1.2.2.6 wrr single register write in some legacy spi devices, a write registers (wrr) command wi th only one data byte would upd ate status register 1 and clear some bits in configuration register 1, in cluding the quad mode bit. this could resu lt in unintended exit from quad mode. the s25fs-s family only updates status register 1 when a single data byte is provided. the configuration register 1 is not modified i n this case. 1.2.2.7 other legacy commands not supported ? autoboot related commands ? bank address related commands ? dual output read ? quad output read ? quad page program (qpp) - replaced by page program in qpi mode ? ddr fast read ? ddr dual i/o read
document number: 002-00368 rev. *j page 7 of 151 S25FS128S s25fs256s 1.2.2.8 new features the fs-s family introduces new features to cypress spi category memories: ? single 1.8v power supply for core and i/o voltage. ? configurable initial read latency (number of dummy cycles) fo r faster initial access time or higher clock rate read commands ? quad peripheral interface (qpi, 4-4-4) read mode in which all transfers are 4 bits wide, including instructions ? jedec jesd216 standard, serial flash discoverable parameters (sfdp) that provide device feature and configuration information. ? evaluate erase status command to determine if the last erase operation on a sector completed successfully. this command can be used to detect incomplete erase due to power loss or other c auses. this command can be helpful to flash file system software in file system recovery after a power loss. ? advanced sector protection (asp) permanent protection. a bit is added to the asp register to provide the option to make protection of the persistent protection bi ts (ppb) permanent. also, wh en one of the two asp protection modes is selected, all o tp configuration bits in all registers are pr otected from further programming so that all otp configuration settings are made perm anent. the otp address space is not protected by the selection of an asp pr otection mode. the fr eeze bit (cr1v[0]) may be used to protect the otp address space. 1.3 glossary bcd (binary coded decimal) a value in which each 4-bit nibb le represents a decimal numeral. command all information transferred between the host system and memory during one period while cs# is low. this includes the instruction (sometimes called an operation code or opcode) and any required address, mode bi ts, latency cycles, or data. ddp (dual die package) two die stacked within the same package to increase the memory capacity of a single package. often also referred to as a multi-chip package (mcp). ddr (double data rate) when input and output are latched on every edge of sck. ecc ecc unit = 16 byte aligned and length data groups in the main flash array and otp array, each of which has its own hidden ecc sy ndrome to enable error correction on each group. flash the name for a type of electrical erase programmable read only memory (eeprom) that erases large blocks of memory bits in parallel, making the erase operation much faster than early eeprom. high a signal voltage level v ih or a logic level representing a binary one (1). instruction the 8-bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). the instruction is always the first 8 bits transferred from host system to the memory in any command. low a signal voltage level ? v il or a logic level representing a binary zero (0). lsb (least significant bit) generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value. msb (most significant bit) generally the left most bit, with the highest or der of magnitude value, within a group of bits of a register or data value. n/a (not applicable) a value is not relevant to situation described. non-volatile no power is needed to maintain data stored in the memory. opn ordering part number. the alphanumeric stri ng specifying the memory device type, density, package, factory non-volatile configurati on, etc. used to select the desired device. page 512-byte or 256-byte aligned and length group of data. the size assigned for a page depends on the ordering part number. pcb printed circuit board.
document number: 002-00368 rev. *j page 8 of 151 S25FS128S s25fs256s 1.4 other resources 1.4.1 cypress flash memory roadmap http://www.cypress. com/flash-roadmap 1.4.2 links to software http://www.cypress.co m/software-and-drivers-cypress-flash-memory 1.4.3 links to application notes http://www.cypress.com/cypressappnotes register bit references are in the format: register_name[bit_number] or register_name[bit_range_msb: bit_range_lsb] sdr (single data rate) when input is latched on the rising edge and output on the falling edge of sck. sector erase unit size; depending on device model and sector location this may be 4 kbytes, 64 kbytes or 256 kbytes. write an operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. when changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified ? as a single operation. the non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data.
document number: 002-00368 rev. *j page 9 of 151 S25FS128S s25fs256s hardware interface serial peripheral i nterface with multiple input / output (spi-mio) many memory devices connect to their host system with separate pa rallel control, address, and data signals that require a large number of signal connections and larger package size. the large number of connections increase power consumption due to so many signals switching and the la rger package increases cost. the s25fs-s family reduces the number of signals for connection to the host system by serially transferring all control, addres s, and data information over 4 to 6 signals. this reduces the cost of the memory package, reduces sig nal switching power, and either reduces the host connection count or frees host connectors for use in pr oviding other features. the s25fs-s family uses the industry standard single-bit serial peripheral interface (spi) and also supports optional extension commands for 2-bit (dual) and 4-bit (quad) wide serial transfers. this multiple width interface is called spi multi-i/o or spi- mio. 2. signal descriptions 2.1 input/output summary signal list signal name type description sck input serial clock. cs# input chip select. si / io0 i/o serial input for single bit data commands or io0 for dual or quad commands. so / io1 i/o serial output for single bit data commands. io 1 for dual or quad commands. wp# / io2 i/o write protect when not in quad mode (cr1v[1] = 0 and sr1nv[7] = 1). io2 when in quad mode (cr1v[1] = 1). the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands or writ e protection. if write protection is enabled by sr1nv[7] = 1 and cr1v[1] = 0, the host system is required to drive wp# high or low during a wrr or wrar command. io3 / reset# i/o io3 in quad-i/o mode, when configuration r egister 1 quad bit, cr1v[1] =1, and cs# is low. reset# when enabled by cr2v[5]=1 and not in quad-i/o mode, cr1v[1] = 0, or when enabled in quad mode, cr1v[1] = 1 and cs# is high. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands or reset#. v cc supply power supply. v ss supply ground. nc unused not connected. no device internal signal is c onnected to the package connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a print ed circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v cc . rfu reserved reserved for future use. no device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. it is recommended to not use rfu connectors for pc b routing channels so that the pcb may take advantage of future enhanced features in compatible footprint devices. dnu reserved do not use. a device internal signal may be c onnected to the package connector. the connection may be used by cypress for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when the signal is at v il . the signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to this connection.
document number: 002-00368 rev. *j page 10 of 151 S25FS128S s25fs256s 2.2 multiple input / output (mio) traditional spi single bit wide commands (single or sio) send info rmation from the host to the me mory only on the serial input (si) signal. data may be sent back to the host serially on the serial output (so) signal. dual or quad input / output (i/o) commands s end instructions to the memory only on the si/io0 signal. address or data is sent f rom the host to the memory as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. data is returned to t he host similarly as bit pairs on io0 and io1 or four bi t (nibble) groups on io 0, io1, io2, and io3. qpi mode transfers all instructions, address, and data from the host to the memory as four bit (n ibble) groups on io0, io1, io2 , and io3. data is returned to the host similarly as fo ur bit (nibble) groups on io0, io1, io2, and io3. 2.3 serial clock (sck) this input signal provides the synchronization reference for the spi interface. instructions, add resses, or data input are latc hed on the rising edge of the sck signal. data output changes after th e falling edge of sck, in sdr commands, and after every edge in ddr commands. 2.4 chip select (cs#) the chip select signal indicates when a command is transferring information to or from the device and the other signals are rel evant for the memory device. when the cs# signal is at the logic high state, the device is not selected and all input signals are ignored and all output sig nals are high impedance. the device will be in the st andby power mode, unless an internal embedded operation is in progress. an embedded operation is indicated by the status register 1 write-in-progress bit (sr1v[1] ) set to 1, until the operation is compl eted. some example embedded operations are: program, erase, or write registers (wrr) operations. driving the cs# input to the logic low state enables the device, placing it in the active powe r mode. after power-up, a falling edge on cs# is required prior to the start of any command. 2.5 serial input (si) / io0 this input signal is used to tr ansfer data serially into the de vice. it receives instructions, a ddresses, and data to be progra mmed. values are latched on the rising edge of serial sck clock signal. si becomes io0 - an input and output during dual and quad comm ands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock sig nal) as well as shifting out data (on the falling edge of sck, in sdr commands, and on every edge of sck, in ddr commands). 2.6 serial output (so) / io1 this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial s ck clock signal. so becomes io1 - an input and output during dual and quad co mmands for receiving addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck, in sdr com mands, and on every edge of sck, in ddr commands). 2.7 write protect (wp#) / io2 when wp# is driven low (v il ), during a wrr or wrar command and while the st atus register write disable (srwd_nv) bit of status register 1 (sr1nv[7]) is set to a 1, it is not possible to writ e to status register 1 or c onfiguration register 1 relate d registers. in this situation, a wrr command is ignored, a wrar command selecting sr1nv, sr1v, cr1nv, or cr1v is ignored, and no error is set. this prevents any alteration of the block pr otection settings. as a consequence, all th e data bytes in the memory area that are protected by the block protection feature ar e also hardware protected against data modification if wp# is low during a wrr or wrar command with srwd_nv set to 1.
document number: 002-00368 rev. *j page 11 of 151 S25FS128S s25fs256s the wp# function is not available when the quad mode is enabled ( cr1v[1] = 1). the wp# function is replaced by io2 for input an d output during quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal ) as well as shifting out data (on the fallin g edge of sck, in sdr commands, and on every edge of sck, in ddr commands). wp# has an internal pull-up resistance; when unconnected, wp# is at v ih and may be left unconnected in the host system if not used for quad mode or protection. 2.8 io3 / reset# io3 is used for input and output during quad mode (cr1v[1] = 1) for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge of sck, in sdr commands, and on eve ry edge of sck, in ddr commands). the io3 / reset# signal may also be used to initiate the hardware reset function when the reset feature is enabled by writing configuration register 2 non-volatile bit 5 (cr2v[5] = 1). the i nput is only treated as reset# wh en the device is not in quad-i /o mode, cr1v[1] = 0, or when cs# is high. when quad i/o mode is in use, cr1v[1]=1, and the device is selected with cs# low, the io3 / reset# is used only as io3 for informa tion transfer. when cs# is high, the io3 / reset# is not in use for information transfe r and is used as the reset# input. by conditioning the reset oper ation on cs# high during quad mode, the reset function remains available during quad mode. when the system enters a reset condition, the cs# signal must be driven high as part of the reset process and the io3 / reset# signal is driven low. when cs# goes high the io3 / reset# input transitions from being io3 to being the reset# input. the reset condition is then detected when cs# remains high and the io3 / reset# signal remains low for t rp . if a reset is not intended, the system is required to actively drive io3 / reset# to high along with cs# being driven high at the end of a transfer of data to th e memory. following transfers of data to the host system, the memo ry will drive io 3 high during t cs . this will ensure that io3 / reset is not left floating or being pulled slowly to high by the internal or an external passive pull-up. thus, an unintended reset i s not triggered by the io3 / reset# not being re cognized as high be fore the end of t rp . the io3 / reset# signal is unused when the reset feature is disabled (cr2v[5] = 0). the io3 / reset# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad mode or the reset function. the internal pull-up will hold io3 / reset high after the host system has actively driven the signal high and then stops driving the signal. note that io3 / reset# cannot be shared by more than one spi-m io memory if any of them are operating in quad i/o mode as io3 being driven to or from one selected memory may look like a reset signal to a second non-selected memory sharing the same io3 / reset# signal. 2.9 voltage supply (v cc ) v cc is the voltage source for all device internal logic. it is th e single voltage used for all devi ce internal func tions including read, program, and erase. 2.10 supply and signal ground (v ss ) v ss is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers. 2.11 not connected (nc) no device internal signal is connected to the package connector no r is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). 2.12 reserved for future use (rfu) no device internal signal is currently connected to the package connector but there is potential future use of the connector. i t is recommended to not use rfu connectors for pcb routing channe ls so that the pcb may take advantage of future enhanced features in compatib le footprint devices.
document number: 002-00368 rev. *j page 12 of 151 S25FS128S s25fs256s 2.13 do not use (dnu) a device internal signal may be connected to the package connecto r. the connection may be used by cypress for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when th e signal is at v il . the signal has an inte rnal pull-down resistor and may be left unconnected in t he host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. 2.14 block diagrams figure 2.1 bus master and memory devices on the spi bus ? single bit data path figure 2.2 bus master and memory devices on the spi bus ? dual bit data path spi bus master reset# wp# so si sck cs2# cs1# fs-s flash fs-s flash reset# wp# so si sck cs2# cs1# spi bus master reset# wp# io1 io0 sck cs2# cs1# fs-s flash fs-s flash reset# wp# io0 io1 sck cs2# cs1#
document number: 002-00368 rev. *j page 13 of 151 S25FS128S s25fs256s figure 2.3 bus master and memory devices on the spi bus ? quad bit data path 3. signal protocols 3.1 spi clock modes 3.1.1 single data rate (sdr) the s25fs-s family can be driven by an embedded microcontroller (b us master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data i s always available from the falling edge of the sck clock signal. the difference between the two modes is t he clock polarity when the bus master is in standby mode and not transferring any data . ? sck will stay at logic low state with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 3.1 spi sdr modes supported timing diagrams throughout the remainder of the document are g enerally shown as both mode 0 and 3 by showing sck as both high and low at the fall of cs#. in some cases a timing diagram ma y show only mode 0 with sck low at the fall of cs#. in such a case, mode 0 timing simply means the clock is high at the fall of cs# so no sck rising edge set up or hold time to the falling edge of cs# is needed for mode 0. sck cycles are measured (counted) from one falling edge of sc k to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already l ow at the beginning of a command. spi bus master io3 / reset# io2 io1 io0 sck cs1# fs-s flash reset# / io3 io2 io0 io1 sck cs1# cpol=0_cpha=0_sck cpol=1_cpha=1_sck cs# si so msb msb
document number: 002-00368 rev. *j page 14 of 151 S25FS128S s25fs256s 3.1.2 double data rate (ddr) mode 0 and mode 3 are also supported for ddr commands. in ddr co mmands, the instruction bits ar e always latched on the rising edge of clock, the same as in sdr commands. however, the addre ss and input data that follow the instruction are latched on both the rising and falling edges of sck. the first address bit is latched on the first rising edge of sck following the falling edg e at the end of the last instruction bit. the first bit of output data is driven on the falling edge at the end of the last access latency ( dummy) cycle. sck cycles are measured (counted) in the same way as in sdr co mmands, from one falling edge of sck to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measur ed from the falling edge of cs# to the fi rst falling edge of sck because sck is already low at the beginning of a command. figure 3.2 spi ddr modes supported 3.2 command protocol all communication between the host system and s25fs-s family memory devices is in the form of units called commands. all commands begin with an 8-bit instructi on that selects the type of information tr ansfer or device operation to be performed. commands may also have an address, instruction modifier, latency per iod, data transfer to the memo ry, or data transfer from the memory. all instruction, address, and data information is tran sferred sequentially between the host system and memory device. command protocols are also classified by a numerical nomenclatur e using three numbers to referenc e the transfer width of three command phases: ? instruction; ? address and instruction modifier (continuous read mode bits); ? data. single bit wide commands start with an instruction and may provide an address or data, all sent only on the si signal. data may be sent back to the host serially on the so signal. this is refere nced as a 1-1-1 command protocol for single bit width instructio n, single bit width address and modifier, single bit data. dual or quad input / output (i/o ) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibb le) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) grou ps on io0, io1, io2, and io3. this is referenced as 1-2-2 fo r dual i/o and 1-4-4 for quad i/o command protocols. the s25fs-s family also supports a qpi mode in which all informa tion is transferred in 4-bit width, including the instruction, address, modifier, and data. this is refer enced as a 4-4-4 command protocol. commands are structured as follows: ? each command begins with cs# going low and ends with cs# returning high. the memory device is selected by the host driving the chip select (cs#) signal low throughout a command. ? the serial clock (sck) marks the transfer of each bi t or group of bits between the host and memory. ? each command begins with an 8-bit (byte) in struction. the instruction selects the type of information transfer or device operat ion to be performed. the instruction transfers occur on sck rising edg es. however, some read commands are modified by a prior read command, such that the instruction is imp lied from the earlier command. this is ca lled continuous read mode. when the device is in continuous read mode, the instruction bits are not transmitted at the beginning of the comma nd because the instruction is th e same as the read command that initiated the continuous read mode. in continuous read mode the command will begin with the read address. thus, continuous read mode removes eight instructi on bits from each read command in a series of same type read commands. cpol=0_cpha=0_sck cpol=1_cpha=1_sck cs# transfer_phase si so inst. 7 inst. 0 a31 a30 a0 m7 m6 m0 dlp7 dlp0 d0 d1 dummy / dlp address mode instruction
document number: 002-00368 rev. *j page 15 of 151 S25FS128S s25fs256s ? the instruction may be stand alone or may be followed by address bi ts to select a location within one of several address spaces in the device. the instruction determines the address space used. the address may be either a 24-bit or a 32-bit, byte boundary , address. the address transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? in legacy spi mode, the width of all transfers following the in struction are determined by the instruction sent. following tran sfers may continue to be single bit serial on only the si or serial ou tput (so) signals, they may be done in two bit groups per (dual ) transfer on the io0 and io1 signals, or they may be done in 4- bit groups per (quad) transfer on the io0-io3 signals. within the dual or quad groups the least significant bit is on io0. more significant bits are placed in significance order on each higher numbe red io signal. single bits or parallel bit groups are tr ansferred in most to least significant bit order. ? in qpi mode, the width of all transfers is a 4-bit wide (quad) transfer on the io0-io3 signals. ? dual and quad i/o read instructions send an instruction modifi er called continuous read mode bits, following the address, to indicate whether the next command will be of the same type with an implied, rather than an explicit, instruction. these mode bi ts initiate or end the continuous read mode. in continuous read mode , the next command thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. the mode bit transfers occur on sc k rising edge, in sdr commands, or on every sck edge, in ddr commands. ? the address or mode bits may be followed by write data to be st ored in the memory device or by a read latency period before read data is returned to the host. ? write data bit transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? sck continues to toggle during any read access latency per iod. the late ncy may be zero to several sck cycles (also referred to as dummy cycles). at the end of the read latency cycles, the first read data bits are driven from the outputs on sck falling ed ge at the end of the last read latency cycle. the first read data bits are consi dered transferred to the ho st on the following sck ri sing edge. each following transfer occurs on the next sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? if the command returns read data to the host, the device continues sending data transfers until the host takes the cs# signal h igh. the cs# signal can be driven high after any transfer in the read data sequence. this will terminate the command. ? at the end of a command that does not retu rn data, the host drives the cs# input high. the cs# signal must go high after the eighth bit, of a stand alone instruction or, of the last write data byte that is transfe rred. that is, the cs# signal must be d riven high when the number of bits after the cs# signal was driven low is an exact multiple of eight bits. if the cs# signal does not go h igh exactly at the eight bit boundary of the instruction or write data, the command is rejected and not executed. ? all instruction, address, and mode bits ar e shifted into the device with the most signi ficant bits (msb) first. the data bits a re shifted in and out of the device msb first. all data is transferred in byte units with the lowest address byte sent first. the following bytes of data are sent in lowest to highest by te address order i.e. the byte address increments. ? all attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will continue to execute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. ? depending on the command, the time for execution varies. a co mmand to read status information from an executing command is available to determine when the command complete s execution and whether the command was successful. 3.2.1 command sequence examples figure 3.3 stand alone instruction command cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00368 rev. *j page 16 of 151 S25FS128S s25fs256s figure 3.4 single bit wide input command figure 3.5 single bit wide output command figure 3.6 single bit wide i/o command without latency figure 3.7 single bit wide i/o command with latency figure 3.8 dual i/o command cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data 2 cs# sck si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data 2 cs# sck si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2
document number: 002-00368 rev. *j page 17 of 151 S25FS128S s25fs256s figure 3.9 quad i/o command figure 3.10 quad i/o read command in qpi mode figure 3.11 ddr quad i/o read figure 3.12 ddr quad i/o read in qpi mode additional sequence diagrams, specific to each command, are provided in commands on page 76 . cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 4 0 4 0 4 0 4 0 4 0 4 0 29 5 1 5 1 5 1 5 1 5 1 5 1 30 6 2 6 2 6 2 6 2 6 2 6 2 31 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 28 4 0 4 0 4 0 4 0 4 0 4 0 5 1 29 5 1 5 1 5 1 5 1 5 1 5 1 6 2 30 6 2 6 2 6 2 6 2 6 2 6 2 7 3 31 7 3 7 3 7 3 7 3 7 3 7 3 instruct. address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address mode dummy dlp d1 d2 cs# sck io0 io1 io2 io3 phase 4 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 5 1 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 6 2 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 7 3 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruct. address mode dummy dlp d1 d2
document number: 002-00368 rev. *j page 18 of 151 S25FS128S s25fs256s 3.3 interface states this section describes the input and output signal levels as related to the spi interface behavior. legend z = no driver - floating signal hl = host driving v il hh = host driving v ih hv = either hl or hh x = hl or hh or z ht = toggling between hl and hh ml = memory driving v il mh = memory driving v ih mv = either ml or mh 3.3.1 power-off when the core supply voltage is at or below the v cc (low) voltage, the device is considered to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. 3.3.2 low-power hardwa re data protection when v cc is less than v cc (cut-off) the memory device will ignore commands to en sure that program and erase operations can not start when the core supply volta ge is out of the operating range. interface states summary interface state v cc sck cs# io3 / reset# wp# / io2 so / io1 si / io0 power-off document number: 002-00368 rev. *j page 19 of 151 S25FS128S s25fs256s 3.3.3 power-on (cold) reset when the core voltage supply remains at or below the v cc (low) voltage for t pd time, then rises to v cc (minimum) the device will begin its power-on reset (por) process. por continues until the end of t pu . during t pu the device does not react to external input signals nor drive any outputs. following the end of t pu the device transitions to the inte rface standby state and can accept commands. for additional information on por see power-on (cold) reset on page 28 3.3.4 hardware (warm) reset a configuration option is provided to allow io3 to be used as a hardware reset input when the device is not in quad mode or whe n it is in quad mode and cs# is high. when io3 / reset# is driven low for t rp time the device starts the hardware reset process. the process continues for t rph time. following the end of both t rph and the reset hold time following the rise of reset# (t rh ) the device transitions to the interface standby state and can accept commands. for additional information on hardware reset see reset on page 28 3.3.5 interface standby when cs# is high the spi interface is in standby state. inputs other than reset# are ignored. th e interface waits for the begin ning of a new command. the next interface state is instruct ion cycle when cs# goes low to begin a new command. while in interface standby state the memory device draws standby current (i sb ) if no embedded algorithm is in progress. if an embedded algorithm is in progress, the related current is drawn unt il the end of the algorithm when the entire device returns t o standby current draw. a deep power-down (dpd) mode is supported by the fs-s family of devices. if the device has been placed in dpd mode by the dpd (b9h) command, the interface standby current is i dpd . the dpd command is accepted only while the device is not performing an embedded operation, as indicated by th e status register-1 volatile write in progress (wip) bit being cleared to zero (sr1v[0]=0). while in dpd mode , the device ignores all commands except the release from dpd (res abh) command, that will return the device to the interface standby state after a delay of t res . 3.3.6 instruction cycl e (legacy spi mode) when the host drives the msb of an instruction and cs# goes low, on the next rising edge of sck the device captures the msb of the instruction that begins the new command. on each following ri sing edge of sck the device captures the next lower significan ce bit of the 8-bit instruction. th e host keeps cs# low, and drives the write protect (w p#) and io3/reset signa ls as needed for th e instruction. however, wp# is only releva nt during instruction cycles of a wrr or wrar command and is otherwise ignored. io3/reset# is driven high when the device is not in quad mode (cr1 v[1] = 0) or qpi mode (cr2v[6] = 0) and hardware reset is not required. each instruction selects the addr ess space that is operated on and the transfer format used during the remainder of the command . the transfer format may be single, dual i/o, quad i/o, or ddr quad i/o. the expected next interface state depends on the instruction received. some commands are stand alone, needing no address or data transfer to or from the memory. the ho st returns cs# high after the rising edge of sck for the eighth bit of the in struction in such commands. the next inte rface state in this case is interface s tandby. 3.3.7 instruction c ycle (qpi mode) in qpi mode, when cr2v[6]=1, instructions are transferred 4 bits per cycle. in this mode, instru ction cycles are the same as a quad input cycle. see quad input cycle - host to memory transfer on page 20 . 3.3.8 single input cycle - host to memory transfer several commands transfer information afte r the instruction on the single serial input (si) signal from host to the memory devi ce. the host keeps reset# high, cs# low, and drives si as needed fo r the command. the memory does not drive the serial output (so) signal. the expected next interface state depends on the instruction. some instructions continue sending address or data to the memory using additional single input cycles. others may transition to si ngle latency, or directly to single, dual, or quad output cycl e states.
document number: 002-00368 rev. *j page 20 of 151 S25FS128S s25fs256s 3.3.9 single latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the conf iguration register (cr2v[3:0]) . during the latency cycles, the host keeps reset# high, cs# low. the write protect (wp#) signal is i gnored. the host may drive t he si signal during these cycles or the host may leave si floating . the memory does not use any data driven on si / i/o0 or other i/ o signals during the latency cycles. the memory does not drive the serial output (so) or i/o signals during the latency cycles. the next interface state depends on the comm and structure i.e. the number of latency cycles, and whether the read is single, du al, or quad width. 3.3.10 single output cycle - memory to host transfer several commands transfer information back to the host on the si ngle serial output (so) signal. the host keeps reset# high, cs# low. the write protect (wp#) signal is ignor ed. the memory ignores the serial input (si) signal. the memory drives so with data . the next interface state continues to be single output cycle until the host returns cs# to high ending the command. 3.3.11 dual input cycle - host to memory transfer the read dual i/o command transfers two address or mode bits to the memory in each cycle. the host keeps reset# high, cs# low. the write protect (wp#) signal is ignored. the host drives address on si / io0 and so / io1. the next interface st ate following the delivery of address a nd mode bits is a dual latency c ycle if there are latency cycles ne eded or dual output cycle if no latency is required. 3.3.12 dual latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the conf iguration register (cr2v[3:0]) . during the latency cycles, the host keeps reset# high, cs# low. the write protect (wp#) signal is i gnored. the host may drive t he si / io0 and so / io1 signals during these cycles or the host ma y leave si / io0 and so / io1 floating. the memory does not use any data driven on si / io0 and so / io1 duri ng the latency cycles. the host must stop driving si / io0 and so / io1 on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving them during all latency cycles so that there is sufficient time for the host driv ers to turn off before the memo ry begins to drive at the end of the latency cycles. this preve nts driver conflict between host and memory when the signal direction cha nges. the memory does not drive the si / io0 and so / io1 signals during the latency cycles. the next interface state fo llowing the last la tency cycle is a du al output cycle. 3.3.13 dual output cycle - memory to host transfer the read dual output and read dual i/o return data to the host two bits in each cycle. the host keeps reset# high, cs# low. the write protect (wp#) signal is ignored. the memory drives data on the si / io0 and so / io1 signals during the dual output cycles. the next interface state continues to be dual output cycl e until the host returns cs# to high ending the command. 3.3.14 quad input cycle - host to memory transfer the quad i/o read command transfers four address or mode bits to the memory in each cycle. in qpi mode the quad i/o read and page program commands transfer four data bits to the memory in each cycle, includi ng the instruction cycles . the host keeps cs# low, and drives the io signals. for quad i/o read the next interface state fo llowing the delivery of address and mode bits is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. for qpi mode page program, the host returns cs# high following the delivery of data to be programme d and the interface retu rns to standby state. 3.3.15 quad latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the conf iguration register (cr2v[3:0]) . during the latency cycles, the host keeps cs# low. the host may drive th e io signals during these cycles or the host may leave the
document number: 002-00368 rev. *j page 21 of 151 S25FS128S s25fs256s io floating. the memory does not use any data driven on io durin g the latency cycles. the host must stop driving the io signals on the falling edge at the end of the last latency cycle. it is re commended that the host stop driving them during all latency cyc les so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. t his prevents driver conflict between host and memory when the signal direction changes. the memory does not drive the io signals during the latency cycles. the next interface state following the la st latency cycle is a quad output cycle. 3.3.16 quad output cycle - memory to host transfer the quad i/o read returns data to the host four bits in each cycl e. the host keeps cs# low. the me mory drives data on io0?io3 signals during the quad output cycles. the next interface state continues to be quad output c ycle until the host returns cs# to high ending the command. 3.3.17 ddr quad input cycle - host to memory transfer the ddr quad i/o read command sends address, and mode bits to the memory on all the io signals . four bits are transferred on the rising edge of sck and four bits on the falling edge in each cycle. the host keeps cs# low. the next interface state following the delivery of address and mode bits is a ddr latency cycle. 3.3.18 ddr latency cycle ddr read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the configur ation register (cr2v[3:0]). during the latency cycles, the host keeps cs# low. the host may not drive the io signals during these cycles. so t hat there is sufficient time for the host drivers to turn off before the memory begins to dr ive. this prevents driver conflict betw een host and memory when the signal direction changes. the memory has an option to drive all the io signals with a data learning pattern (dlp) during the last 4 latency cycles. t he dlp option should not be enabled when there are fewer than five latency cycles so t hat there is at least one cycle of high impeda nce for turn around of the io signals before the memory begins driving the dlp. when there are more than 4 cycles of latency the memory does not drive the io signals unt il the last four cycles of latency. the next interface state following the last latency cycle is a ddr single, or quad output cycle, depending on the instruction. 3.3.19 ddr quad output cycle - memory to host transfer the ddr quad i/o read command returns bits to the host on all t he io signals. four bits are transferred on the rising edge of s ck and four bits on the falling edge in each cycle. the host keeps cs# low. the next interface state continues to be ddr quad output cycle until the host returns cs# to high ending the command. 3.4 configuration register effects on the interface the configuration register 2 volatile bits 3 to 0 (cr2v[3:0]) select the variable late ncy for all array read commands except re ad and read sdfp (rsfdp). read always has zero laten cy cycles. rsfdp always has 8 latency cycles. the variable latency is also used in the otpr, eccrd, and rdar commands. the configuration regi ster bit 1 (cr1v[1]) select s whether quad mode is enabled to swit ch wp# to io2 function, reset# to io3 function, and thus allow quad i/o read and qpi mode commands. quad mode must also be selected to allow ddr quad i/o read commands. 3.5 data protection some basic protection against unintended changes to stored data are provided and controlled purel y by the hardware design. thes e are described below. other software managed protection method s are discussed in the software section of this document.
document number: 002-00368 rev. *j page 22 of 151 S25FS128S s25fs256s 3.5.1 power-up when the core supply voltage is at or below the v cc (low) voltage, the device is considered to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. program and erase operations contin ue to be prevented during the power-on reset (por) because no comm and is accepted until the exit from por to the interface standby state. 3.5.2 low power when v cc is less than v cc (cut-off) the memory device will ignore commands to en sure that program and erase operations can not start when the core supply volta ge is out of the operating range. 3.5.3 clock pulse count the device verifies that all non-volatile memory and register da ta modifying commands consist of a clock pulse count that is a multiple of eight bit transfers (byte boundar y) before executing them. a command not ending on an 8-bit (byte) boundary is igno red and no error status is set for the command. 3.5.4 deep power-down (dpd) in dpd mode, the device responds only to the release from dpd command (res abh). all other commands are ignored during dpd mode, thereby protecting the memory from program and erase operations. 4. electrical specifications 4.1 absolute maximum ratings notes: 1. see section 4.4.3, input signal overshoot on page 23 for allowed maximums during signal transition. 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 thermal resistance absolute maximum ratings storage temperature plastic packages ?65 c to +150 c ambient temperature with power applied ?65 c to +125 c v cc ?0.5 v to +2.5 v input voltage with respect to ground (v ss ) (note 1) ?0.5 v to v cc + 0.5 v output short circuit current (note 2) 100 ma thermal resistance parameter description soc008 wnd008 fab024 fac024 unit theta ja thermal resistance (junction to ambient) 75 18 39 39 c
document number: 002-00368 rev. *j page 23 of 151 S25FS128S s25fs256s 4.3 latch-up characteristics note: 1. excludes power supply v cc . test conditions: v cc = 1.8 v, one connection at a time tested, connections not being tested are at v ss . 4.4 operating ranges operating ranges define those limit s between which the functionalit y of the device is guaranteed. 4.4.1 power supply voltages v cc ????????????........... ............ ........ 1.7 v to 2.0 v 4.4.2 temperature ranges note: 1. industrial plus operating and performance parameters will be determi ned by device characterization and may vary from standard industrial temperature range devices as currently shown in this specification. 4.4.3 input sign al overshoot during dc conditions, input or i/o signals should remain equal to or between v ss and v cc . during voltage transitions, inputs or i/os may overshoot v ss to -1.0v or overshoot to v cc + 1.0 v, for periods up to 20 ns. figure 4.1 maximum negative overshoot waveform latch-up specification description min max unit input voltage with respect to v ss on all input only connections -1.0 v cc + 1.0 v input voltage with respect to v ss on all i/o connections -1.0 v cc + 1.0 v v cc current -100 +100 ma parameter symbol device spec unit min max ambient temperature t a industrial (i) -40 +85 c industrial plus (v) -40 +105 c automotive, aec-q100 grade 3 (a) -40 +85 c automotive, aec-q100 grade 2 (b) -40 +105 c automotive, aec-q100 grade 1 (m) -40 +125 c v ss to v cc - 1.0v 20 ns
document number: 002-00368 rev. *j page 24 of 151 S25FS128S s25fs256s figure 4.2 maximum positive overshoot waveform 4.5 power-up and power-down the device must not be selected at power-up or power- down (that is, cs# must follo w the voltage applied on v cc ) until v cc reaches the correct value as follows: ? v cc (min) at power-up, and then for a further delay of t pu ? v ss at power-down a simple pull-up resistor on chip select (cs#) can usually be used to insure safe and proper power-up and power-down. the device ignores all instructions until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold (see figure 4.3 ). however, correct operation of the device is not guaranteed if v cc returns below v cc (min) during t pu . no command should be sent to the device until the end of t pu . the device draws i por during t pu . after power-up (t pu ), the device is in standby mode, draws cmos standby current (i sb ), and the wel bit is reset. during power-down or voltage drops below v cc (cut-off), the voltage must drop below v cc (low) for a period of t pd for the part to initialize correctly on power-up. see figure 4.4 . if during a voltage drop the v cc stays above v cc (cut-off) the part will stay initialized and will work correctly when v cc is again above v cc (min). in the event power-on reset (por ) did not complete correctly after power-up, the assertion of the reset# signal or receiving a software rese t command (reset) will restart the por process. normal precautions must be taken for supply rail decoupling to stabilize the v cc supply at the device. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the pa ckage supply connection (this ca pacitor is generally of the order of 0.1 f). fs-s power-up / power-down voltage and timing symbol parameter min max unit v cc (min) v cc (minimum operation voltage) 1.7 v v cc (cut-off) v cc (cut 0ff where re-initialization is needed) 1.5 v v cc (low) v cc (low voltage for initialization to occur) 0.7 v t pu v cc (min) to read operation 300 s t pd v cc (low) time 10.0 s v cc + 1.0v 20 ns v ss to v cc
document number: 002-00368 rev. *j page 25 of 151 S25FS128S s25fs256s figure 4.3 power-up figure 4.4 power-down and voltage drop tpu full device access v cc (min) v cc (max) time v cc (max) v cc (min) v cc (cut-off) v cc (low) tpu device access allowed no device access allowed tpd time
document number: 002-00368 rev. *j page 26 of 151 S25FS128S s25fs256s 4.6 dc characteristics applicable within operating ranges. notes: 1. typical values are at t ai = 25 c and v cc = 1.8 v. 2. outputs unconnected during read data return. output switching current is not included. 4.6.1 active power and standby power modes the device is enabled and in the active power mode when chip se lect (cs#) is low. when cs# is high, the device is disabled, but may still be in an active power mode until all program, erase, and write operations have complete d. the device then goes into t he standby power mode, and powe r consumption drops to i sb . a deep power-down (dpd) mode is supported by the fs-s family of devices. if the device has been placed in dpd mode by the dpd (b9h) command, the interface standby current is i dpd . the dpd command is accepted only while the device is not performing an embedded operation as indicated by the status register-1 volatile write in pr ogress (wip) bit being cleared to zero (sr1v[0] = 0). while in dpd mode, the device ignores all comm ands except the release from dp d (res abh) command, that will return the device to the interface standby state after a delay of t res . fs-s dc characteristics symbol parameter test conditions min typ (1) max unit v il input low voltage -0.5 0.3xv dd v v ih input high voltage 0.7xv dd v cc +0.4 v v ol output low voltage i ol = 0.1 ma 0.2 v v oh output high voltage i oh = ?0.1 ma v cc - 0.2 v i li input leakage current v cc = v cc max, v in = v ih or v ss , cs# = v ih 2 a i lo output leakage current v cc = v cc max, v in = v ih or v ss , cs# = v ih 2 a i cc1 active power supply current (read) (2) serial sdr @ 50 mhz serial sdr @ 133 mhz quad sdr @ 133 mhz quad ddr @ 80 mhz 10 25 60 70 18 30 65 90 ma i cc2 active power supply current (page program) cs# = v cc 60 100 ma i cc3 active power supply current (wrr or wrar) cs# = v cc 60 100 ma i cc4 active power supply current (se) cs# = v cc 60 100 ma i cc5 active power supply current (be) cs# = v cc 60 100 ma i sb standby current io3/reset#, cs# = v cc ; si, sck = v cc or v ss , industrial temp/automotive, aec-q100 grade 3 25 100 a i sb standby current io3/reset#, cs# = v cc ; si, sck = v cc or v ss , industrial plus temp/automotive, aec-q100 grade 2 25 300 a i sb standby current io3/reset#, cs# = v cc ; si, sck = v cc or v ss , automotive, aec-q100 grade 1 25 300 a i dpd deep power-down current io3/reset#, cs# = v cc ; si, sck = v cc or v ss , industrial temp/automotive, aec-q100 grade 3 650a i dpd deep power-down current io3/reset#, cs# = v cc ; si, sck = v cc or v ss , industrial plus temp/automotive, aec-q100 grade 2 6100a i dpd deep power-down current io3/reset#, cs# = v cc ; si, sck = v cc or v ss , automotive, aec-q100 grade 1 6170a i por power-on reset current io3/reset#, cs# = v cc ; si, sck = v cc or v ss 80 ma
document number: 002-00368 rev. *j page 27 of 151 S25FS128S s25fs256s 5. timing specifications 5.1 key to switching waveforms figure 5.1 waveform element meanings 5.2 ac test conditions figure 5.2 test setup notes: 1. input slew rate measured from input pulse min to max at v cc max. example: (1.9 v x 0.8) - (1.9 v x 0.2) = 1.14 v; 1.14 v/1.25 v/ns = 0.9 ns rise or fall time. 2. ac characteristics tables assume clock and data signals have the same slew rate (slope). figure 5.3 input, output, and timing reference levels ac measurement conditions symbol parameter min max unit c l load capacitance 30 pf input pulse voltage 0.2 v cc 0.8 v cc v input slew rate 0.23 1.25 v/ns input rise and fall times 0.9 5 ns input timing ref voltage 0.5 v cc v output timing ref voltage 0.5 v cc v input symbol output valid at logic high or low high impedance any change permitted logic high logic low high impedance changing, state unknown logic high logic low valid at logic high or low device under test c l v cc + 0.4v 0.7 x v cc 0.3 x v cc - 0.5v timing reference level 0.5 x v cc v cc - 0.2v 0.2v input levels output levels
document number: 002-00368 rev. *j page 28 of 151 S25FS128S s25fs256s 5.2.1 capacitance characteristics note: 1. parameter values are not 100% tested. for more details, please refer to the ibis models. 5.3 reset 5.3.1 power-on (cold) reset the device executes a power-on reset (por) process until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 4.3, power-up on page 25 , and fs-s power-up / power-down voltage and timing on page 24 . the device must not be selected (cs# to go high with v cc ) during power-up (t pu ), i.e. no commands may be sent to the device until the end of t pu . the io3 / reset# signal functions as the reset# input when cs# is high for more than t cs time or when quad mode is not enabled cr1v[1] = 0. reset# is ignored during por. if reset # is low during por and remains low through and beyond the end of t pu , cs# must remain high until t rh after reset# returns high. reset# must return high for greater than t rs before returning low to initiate a hardware reset. figure 5.4 reset low at the end of por figure 5.5 reset high at the end of por capacitance parameter test conditions min max unit c in input capacitance (applies to sck, cs#, io3/reset#) 1 mhz 8 pf c out output capacitance (applies to all i/o) 1 mhz 8 pf vcc reset# cs# if reset# is low at tpu end cs# must be high at tpu end tpu trh vcc reset# cs# if reset# is high at tpu end cs# may stay high or go low at tpu end tpu tpu
document number: 002-00368 rev. *j page 29 of 151 S25FS128S s25fs256s figure 5.6 por followed by hardware reset 5.3.2 io3 / reset# input initiated hardware (warm) reset the io3 / reset# signal functions as the reset# input when cs# is high for more than t cs time or when quad mode is not enabled cr1v[1] = 0. the io3 / reset# input has an internal pull-up to v cc and may be left unconnected if quad mode is not used. the t cs delay after cs# goes high gives the memory or host system ti me to drive io3 high after its use as a quad mode i/o signal while cs# was low. the internal pull-up to v cc will then hold io3 / reset# high until the host system begins driving io3 / reset#. the io3 / reset# input is ignored while cs# remains high during t cs , to avoid an unintended reset operation. if cs# is driven low to start a new command, io3 / reset# is used as io3. when the device is not in quad mode or, when cs# is high, and io3 / reset# transitions from v ih to v il for > t rp , following t cs , the device will reset register states in the same manner as powe r-on reset but, does not go through the full reset process that is performed during por. the hardware reset process requires a period of t rph to complete. if the por process did not complete correctly for any reason during power-up (t pu ), reset# going low will initiate the full por process instead of the hardware reset process and will require t pu to complete the por process. the reset command is independent of the state of io3 / reset #. if io3 / reset# is high or unconnected, and the reset instruction is issued, the device will perform software reset. additional io3 reset# notes: ? io3 / reset# must be high for t rs following t pu or t rph , before going low again to initiate a hardware reset. ? when io3 / reset# is driven low for at least a minimum period of time (t rp ), following t cs , the device terminates any operation in progress, makes all outputs high impedance, and igno res all read/write commands for the duration of t rph . the device resets the interface to standby state. ? if quad mode and the io3 / reset# feature are enabled , the host system should not drive io3 low during t cs, to avoid driver contention on io3. immediately following commands that transfer data to the host in quad mode, e. g. quad i/o read, the memory drives io3 / reset high during t cs, to avoid an unintended reset operation. immediately following commands that transfer data to the memory in quad mode, e.g. page program, the host system shou ld drive io3 / reset high during t cs, to avoid an unintended reset operation. ? if quad mode is not enabled, and if cs# is low at the time io3 / reset# is asserted low, cs# must return high during t rph before it can be asserted low again after t rh . notes: 1. io3 / reset# low is ignored during power-up (t pu ). if reset# is asserted during the end of t pu , the device will remain in the reset state and t rh will determine when cs# may go low. 2. if quad mode is enabled, io3 / reset# low is ignored during t cs . 3. sum of t rp and t rh must be equal to or greater than t rph . hardware reset parameters parameter description limit time unit t rs reset setup - prior reset end and reset# high before reset# low min 50 ns t rph reset pulse hold - reset# low to cs# low min 35 s t rp reset# pulse width min 200 ns t rh reset hold - reset# high before cs# low min 50 ns vcc reset# cs# trs tpu tpu
document number: 002-00368 rev. *j page 30 of 151 S25FS128S s25fs256s figure 5.7 hardware reset when quad mode is not enabled and io3 / reset# is enabled figure 5.8 hardware reset when quad mode and io3 / reset# are enabled 5.4 sdr ac characteristics ac characteristics symbol parameter min typ max unit f sck, r sck clock frequency for read and 4read instructions dc 50 mhz f sck, c sck clock frequency for fast_read, 4fast_read, and the following dual and quad commands: qor, 4qor, dior, 4dior, qior, 4qior dc 133 mhz f sck, d sck clock frequency for the following ddr commands: qior, 4qior dc 80 mhz p sck sck clock period 1/ f sck ? t wh , t ch clock high time 50% p sck -5% 50% p sck +5% ns t wl , t cl clock low time 50% p sck -5% 50% p sck +5% ns t crt , t clch clock rise time (slew rate) 0.1 v/ns t cft , t chcl clock fall time (slew rate) 0.1 v/ns t cs cs# high time (read instructions) cs# high time (read instructions when reset feature and quad mode are both enabled) cs# high time (program/erase instructions) 10 20 (5) 50 ns t css cs# active setup time (relative to sck) 2 ns t csh cs# active hold time (relative to sck) 3 ns t su data in setup time 2 ns t hd data in hold time 3 ns t v clock low to output valid 8 (2) 6 (3) ns t ho output hold time 1 ns t dis output disable time (4) output disable time (when reset feature and quad mode are both enabled) 8 20 (5) ns t wps wp# setup time (1) 20 ns t wph wp# hold time (1) 100 ns t dpd cs# high to power-down mode 3s t res cs# high to standby mode without electronic signal read 30 s io3_reset# cs# any prior reset trs trp trh trh trph trph io3_reset# cs# reset pulse prior access using io3 for data trp trh trph tc s tdis
document number: 002-00368 rev. *j page 31 of 151 S25FS128S s25fs256s notes: 1. only applicable as a constraint for wrr or wrar instruction when srwd is set to a 1. 2. full v cc range and cl = 30 pf. 3. full v cc range and cl = 15 pf. 4. output high-z is defined as the point where data is no longer driven. 5. t cs and t dis require additional time when the reset feature and quad mode are enabled (cr2v[5] = 1 and cr1v[1] = 1). 5.4.1 clock timing figure 5.9 clock timing 5.4.2 input / output timing figure 5.10 spi single bit input timing figure 5.11 spi single bit output timing v il max v ih min tch tcrt tcft tcl v cc / 2 p sck cs# sck si so msb in lsb in tcss tcss tcsh tcsh tcs tsu thd cs# sck si so msb out lsb out tcs tho tv tdis
document number: 002-00368 rev. *j page 32 of 151 S25FS128S s25fs256s figure 5.12 spi sdr mio timing figure 5.13 wp# input timing 5.5 ddr ac characteristics . note: 1. cl = 15 pf. ac characteristics symbol parameter min typ max unit f sck, r sck clock frequency for ddr read instruction dc 80 mhz p sck, r sck clock period for ddr read instruction 1/f sck ? ns t wh , t ch clock high time 45% p sck ns t wl , t cl clock low time 45% p sck ns t cs cs# high time (read instructions) cs# high time (read instructions when reset feature is enabled) 10 20 ns t css cs# active setup time (relative to sck) 2 ns t csh cs# active hold time (relative to sck) 3 ns t su io in setup time 1.5 ns t hd io in hold time 1.5 ns t v clock low to output valid 1.5 6 (1) ns t ho output hold time 1.5 ns t dis output disable time output disable time (when reset feature is enabled) 8 20 ns t o_skew first output to last output data valid time 600 ps t dpd cs# high to power-down mode 3s t res cs# high to standby mode without electronic signal read 30 s cs# sck io msb in lsb in msb out lsb out tcsh tcsh tcss tcss tsu thd tho tcs tdis tv tv cs# wp# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 wrr or wrar instruction input data twps twph
document number: 002-00368 rev. *j page 33 of 151 S25FS128S s25fs256s 5.5.1 ddr input timing figure 5.14 spi ddr input timing 5.5.2 ddr output timing figure 5.15 spi ddr output timing figure 5.16 spi ddr data valid window notes: 1. t clh is the shorter duration of t cl or t ch . 2. t o_skew is the maximum difference (delta) between the minimum and maximum t v (output valid) across all io signals. cs# sck si_or_io so msb in lsb in tcss tcss tcsh tcsh tcs tsu tsu thd thd cs# sck si so_or_io msb lsb tcs tho tv tv tdis io0 io1 io2 io_valid io3 tdv slow d1 slow d2 fast d1 fast d2 tv to_skew tv sck d1 valid tott tch tcl tdv d2 valid p sck
document number: 002-00368 rev. *j page 34 of 151 S25FS128S s25fs256s 3. t ott is the maximum output transition time from one valid data value to the next valid data value on each io. 4. t ott is dependent on system level considerations including: a. memory device output impedance (drive strength) b. system level parasitics on the ios (primarily bus capacitance) c. host memory controller input v ih and v il levels at which 0 to 1 and 1 to 0 transitions are recognized d. as an example, assuming that the above considerations result a memory output slew rate of 2 v/ns and a 1.8 v transition (from 1 to 0 or 0 to 1) is required by the host, the t ott would be: i. t ott = 1.8 v/(2 v/ns) = 0.9 ns e. t ott is not a specification tested by cypres s, it is system dependent and must be de rived by the system designer based on the above considerations. 5. the minimum data valid window (t dv ) can be calculated as follows: a. as an example, assuming: i. 80 mhz clock frequency = 12.5 ns clock period ii. ddr operations are specified to have a duty cycle of 45% or higher iii. t clh = 0.45*psck = 0.45x12.5 ns = 5.625 ns iv. t o_skew = 400 ps v. t ott = 0.9 ns b. t dv = t clh - t o_skew - t ott c. t dv = 5.625 ns - 400 ps - 0.9 ns = 4.125 ns
document number: 002-00368 rev. *j page 35 of 151 S25FS128S s25fs256s 6. physical interface 6.1 soic 16-lead package 6.1.1 soic 16 connection diagram figure 6.1 16-lead soic package (so3016), top view note: 1. the reset# input has an internal pull-up and may be left unconn ected in the system if quad mode and hardware reset are not in use. 1 2 3 4 16 15 14 13 io3/reset# vcc rfu nc dnu rfu si/io0 sck 5 6 7 8 12 11 10 9 wp#/io2 vss dnu dnu nc rfu cs# so/io1
document number: 002-00368 rev. *j page 36 of 151 S25FS128S s25fs256s 6.1.2 soic 16 physical diagram figure 6.2 soic 16-lead, 300-mil body width (so3016) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date 0.33 c 0.25 m d ca-b 0.20 c a-b 0.10 c 0.10 c 0.10 c d 2x 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 1. all dimensions are in millimeters. notes: d and e1 dimensions are determined at datum h. flash, but inclusive of any mismatch between the top and bottom of exclusive of mold flash, tie bar burrs, gate burrs and interlead 4. the package top may be smaller than the package bottom. dimensions 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified 7. the dimensions apply to the flat section of the lead between 0.10 to maximum material condition. the dambar cannot be located on the 8. dimension "b" does not include dambar protrusion. allowable dambar lower radius of the lead foot. identifier must be located within the index area indicated. 9. this chamfer feature is optional. if it is not present, then a pin 1 10. lead coplanarity shall be within 0.10 mm as measured from the h 0 d l2 n e a1 b c e e1 a 0.75 10.30 bsc 1.27 bsc 0.30 10.30 bsc 0.33 0 0.25 16 0.20 7.50 bsc 0.10 0.31 8 0.51 2.65 2.35 a2 2.05 2.55 b1 0.27 0.48 0.30 0.20 c1 l1 0.40 l 1.27 1.40 ref 0.25 bsc 0 5 15 0 0 1 2 - dimensions symbol min. nom. max. - - - - - - - - - - - - mold flash, protrusions or gate burrs shall not exceed 0.15 mm per d and e1 are determined at the outmost extremes of the plastic body 0.25 mm from the lead tip. protrusion shall be 0.10 mm total in excess of the "b" dimension at the plastic body. package length. seating plane. so3016 kota besy 24-oct-16 24-oct-16 *a 002-15547 package outline, 16 lead soic 12 to fit 10.30x7.50x2.65 mm so3016/sl3016/ss3016 sl3016 ss3016
document number: 002-00368 rev. *j page 37 of 151 S25FS128S s25fs256s 6.2 8-connector packages 6.2.1 8-connector diagrams figure 6.3 8-pin plastic small outline package (soic8) figure 6.4 8-connector package (wson 6x5), top view note: 1. the reset# input has an internal pull-up and may be left unconn ected in the system if quad mode and hardware reset are not in use. 1 2 3 4 8 7 6 5 cs# so / io1 wp# / io2 vss si / io0 sck io3 / reset# vcc soic 1 2 3 4 5 6 7 8 cs# so/io1 io3/reset # sck si/io0 wson wp#/io2 vcc vss
document number: 002-00368 rev. *j page 38 of 151 S25FS128S s25fs256s 6.2.2 8-connector physical diagrams figure 6.5 soic 8-lead, 208 mil body width (soc008) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date 5.28 bsc d 0.51 2 0 1 0 0 n l1 l2 e1 l e e 15 0 5 8 0.76 5.28 bsc 8.00 bsc 1.36 ref 0.25 bsc 8 1.27 bsc 1.70 1.75 0.05 0.33 0.36 0.15 0.19 c1 c b1 b a2 a1 a 1.90 2.16 0.25 0.48 0.46 0.20 0.24 0-8 ref 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 1. all dimensions are in millimeters. notes: d and e1 dimensions are determined at datum h. flash, but inclusive of any mismatch between the top and bottom of exclusive of mold flash, tie bar burrs, gate burrs and interlead 4. the package top may be smaller than the package bottom. dimensions 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified 7. the dimensions apply to the flat section of the lead between 0.10 to maximum material condition. the dambar cannot be located on the 8. dimension "b" does not include dambar protrusion. allowable dambar lower radius of the lead foot. identifier must be located within the index area indicated. 9. this chamfer feature is optional. if it is not present, then a pin 1 10. lead coplanarity shall be within 0.10 mm as measured from the mold flash, protrusions or gate burrs shall not exceed 0.15 mm per d and e1 are determined at the outmost extremes of the plastic body 0.25 mm from the lead tip. protrusion shall be 0.10 mm total in excess of the "b" dimension at the plastic body. package length. seating plane. dimensions symbol min. nom. max. - - - - - - - - - - kota besy 18-jul-16 18-jul-16 ** 12 to fit soc008 002-15548 package outline, 8 lead soic 5.28x5.28x2.16 mm soc008
document number: 002-00368 rev. *j page 39 of 151 S25FS128S s25fs256s figure 6.6 wson 8-contact 6x5 mm leadless (wnd008) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date a maximum 0.15mm pull back (l1) may be present. bilateral coplanarity zone applies to the exposed heat sink pin #1 id on top will be located within the indicated zone. maximum allowable burr is 0. 076mm in all directions. dimension "b" applies to metallized terminal and is measured n is the total number of terminals. all dimensions are in millimeters. dimensioning and tolerancing conforms to asme y14.5m-1994. notes: max. package warpage is 0.05mm. 8 7. 6. 5 2. 4 3. 1. 9 10 the optional radius on the other end of the terminal, the dimension "b" should not be measured in that radius area. nd refers to the number of terminals on d side. 8 4 1.27 bsc. 0.40 6.00 bsc 5.00 bsc 4.00 3.40 0.20 min. 0.75 0.02 0.60 a1 k a e2 d e d2 b l nd n e 0.00 3.30 0.70 3.90 0.35 0.55 3.50 0.05 0.80 4.10 0.45 0.65 a3 0.20 ref dimensions symbol min. nom. max. between 0.15 and 0.30mm from terminal tip. if the terminal has slug as well as the terminals. kota lksu 13-feb-17 13-feb-17 ** 12 to fit wnd008 002-18755 package outline, 8 lead dfn 5.0x6.0x0.8 mm wnd008 4.0x3.4 mm epad (sawn)
document number: 002-00368 rev. *j page 40 of 151 S25FS128S s25fs256s figure 6.7 wson 8-contact 6x8 mm leadless (wnh008) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date jedec specification no. ref. : n/a coplanarity zone applies to the exposed heat sink pin #1 id on top will be located within the indicated zone. dimension "b" applies to metallized terminal and is measured n is the total number of terminals. all dimensions are in millimeters. notes: 5 4 1. 3 2. 6 7. the optional radius on the other end of the terminal, the dimension "b" should not be measured in that radius area. nd refers to the number of terminals on d side. 8 4 1.27 bsc. 0.40 8.00 bsc 6.00 bsc 4.00 3.40 0.20 0.75 - 0.50 a1 k a e2 d e d2 b l nd n e 0.00 3.30 0.70 3.90 0.35 0.45 3.50 0.05 0.80 4.10 0.45 0.55 a3 0.20 ref dimensions symbol min. nom. max. between 0.15 and 0.30mm from terminal tip. if the terminal has slug as well as the terminals. -- kota besy 22-nov-16 22-nov-16 *a 12 to fit wnh008 002-15552 package outline, 8 lead dfn 6.0x8.0x0.8 mm wnh008 4.0x3.4 mm epad (sawn)
document number: 002-00368 rev. *j page 41 of 151 S25FS128S s25fs256s 6.3 fab024 24-ball bga package 6.3.1 connection diagrams figure 6.8 24-ball bga, 5x5 ball f ootprint (fab024), top view notes: 1. signal connections are in the same relati ve positions as fac024 bga, allowing a si ngle pcb footprint to use either package. 2. the reset# input has an internal pull-up and may be left unconn ected in the system if quad mode and hardware reset are not in use. 3 25 4 1 nc nc nc rfu b d e a c vss sck nc vcc dnu rfu cs# nc wp#/io2 dnu si/io0 so/io1 nc io3/ reset# dnu nc nc nc rfu nc
document number: 002-00368 rev. *j page 42 of 151 S25FS128S s25fs256s 6.3.2 physical diagram figure 6.9 ball grid array 24-ball 6x8 mm (fab024) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date metallized mark indentation or other means. a1 corner to be identified by chamfer, laser or ink mark, n is the number of populated solder ball positions for matrix size md x me. when there is an even number of solder balls in the outer row, "sd" = ed/2 and when there is an odd number of solder balls in the outer row, "sd" or "se" = 0. position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and define the symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. e represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a plane ball position designation per jep95, section 3, spp-020. dimensioning and tolerancing methods per asme y14.5m-1994. "+" indicates the theoretical center of depopulated balls. 8. 9. 7 all dimensions are in millimeters. parallel to datum c. 5. 6 4. 3. 2. 1. notes: sd b ed ee me n 0.35 0.00 bsc 1.00 bsc 1.00 bsc 0.40 24 5 0.45 d1 md e1 e d a a1 0.20 - 4.00 bsc 4.00 bsc 5 6.00 bsc 8.00 bsc - - 1.20 - se 0.00 bsc dimensions symbol min. nom. max. "se" = ee/2. fab024 kota besy 18-jul-16 18-jul-16 ** 002-15534 package outline, 24 ball fbga 12 to fit 8.0x6.0x1.2 mm fab024
document number: 002-00368 rev. *j page 43 of 151 S25FS128S s25fs256s 6.4 fac024 24-ball bga package 6.4.1 connection diagram figure 6.10 24-ball bga, 4x6 ball footprint (fac024), top view notes: 1. signal connections are in the same relati ve positions as fab024 bga, allowing a si ngle pcb footprint to use either package. 2. the reset# input has an internal pull-up and may be left unconn ected in the system if quad mode and hardware reset are not in use. 3 24 1 nc nc rfu b d e a c vss sck vcc dnu rfu cs# wp#/io2 dnu si/io0 so/io1 io3/ reset# dnu nc nc rfu nc nc nc nc nc nc f
document number: 002-00368 rev. *j page 44 of 151 S25FS128S s25fs256s 6.4.2 physical diagram figure 6.11 ball grid array 24-ball 6 x 8 mm (fac024) 6.4.3 special handl ing instructions for fbga packages flash memory devices in bga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date metallized mark indentation or other means. a1 corner to be identified by chamfer, laser or ink mark, n is the number of populated solder ball positions for matrix size md x me. when there is an even number of solder balls in the outer row, "sd" = ed/2 and when there is an odd number of solder balls in the outer row, "sd" or "se" = 0. position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and define the symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. e represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a plane ball position designation per jep95, section 3, spp-020. dimensioning and tolerancing methods per asme y14.5m-1994. "+" indicates the theoretical center of depopulated balls. 8. 9. 7 all dimensions are in millimeters. parallel to datum c. 5. 6 4. 3. 2. 1. notes: sd b ed ee me n 0.35 0.50 bsc 1.00 bsc 1.00 bsc 0.40 24 4 0.45 d1 md e1 e d a a1 0.25 - 5.00 bsc 3.00 bsc 6 6.00 bsc 8.00 bsc - - 1.20 - se 0.50 bsc dimensions symbol min. nom. max. "se" = ee/2. fac024 kota besy 18-jul-16 18-jul-16 ** 002-15535 package outline, 24 ball fbga 12 to fit 8.0x6.0x1.2 mm fac024
document number: 002-00368 rev. *j page 45 of 151 S25FS128S s25fs256s software interface this section discusses the features and behavi ors most relevant to host system software that interacts with s25fs-s family memo ry devices. 7. address space maps 7.1 overview 7.1.1 extended address the s25fs-s family supports 32-bit (4-byte) addresses to enab le higher density devices than allowed by previous generation (legacy) spi devices that supported only 24-bit (3-byte) addresse s. a 24-bit, byte resolution, address can access only 16-mbyte s (128-mbits) maximum density. a 32 -bit, byte resolution, address allows direct addre ssing of up to a 4-gbytes (32-gbits) address space. legacy commands continue to support 24-bit addresses for backwa rd software compatibility. extended 32-bit addresses are enabled in two ways: ? extended address mode ? a volatile configur ation register bit that changes all legacy commands to expect 32 bits of address supplied from the host system. ? 4-byte address commands ? that perform both legacy an d new functions, which always expect 32-bit address. the default condition for extended address mode, after power-up or reset, is controlled by a non- volatile configuration bit. th e default extended address mode may be set for 24- or 32-bit addresse s. this enables legacy software compatible access to the fir st 128 mbits of a device or for the device to start directly in 32-bit address mode. the 128-mbit density member of the s25fs- s family supports the extended address features in the same way but in essence ignores bits 31 to 24 of any address because the main flash array only needs 24 bits of address. this enables simple migration from the 128-mb density to higher density devices without changing the address handling aspects of software. 7.1.2 multiple address spaces many commands operate on the main flash memory array. some commands operate on address spaces separate from the main flash array. each separate address space uses the full 24- or 32 -bit address but may only define a small portion of the availab le address space. 7.2 flash memory array the main flash array is divided into erase units called physical sectors. the fs-s family physical sectors may be c onfigured as a hybrid combination of eight 4- kb parameter sectors at the top or bottom of the address space with all but one of the re maining sectors being uniform size. because the group of eight 4-kb parameter secto rs is in total smaller than a uniform sector, the group of 4-kb ph ysical sectors respectively overlay (replace) the top or bottom 32 kb of the highest or lowest address uniform sector. the parameter sector erase commands (20h or 21h) must be used to erase the 4-kb sectors indi vidually. the sector (uniform block) erase commands (d8h or dch) must be used to erase any of the remaining sectors, including the portion of highest or lowe st address sector that is not overlaid by th e parameter sectors. the uniform block erase command has no effect on parameter sector s. configuration register 1 non-volatile bit 2 (cr1nv[2]) equal to 0 overlays the parameter sectors at the bottom of the lowest ad dress uniform sector. cr1nv[2] = 1 overlays the parameter sector s at the top of the highest address uniform sector. see section 7.6, registers on page 50 for more information. there is also a configuration option to re move the 4-kb parameter sectors from the address map so that al l sectors are uniform size. configuration register 3 volatile bit 3 (cr3v[3]) equal to 0 sele cts the hybrid sector architectu re with 4-kb parameter sectors . cr3v[3]=1 selects the uniform sector architecture without parame ter sectors. uniform physical sectors are 64 kb in fs128s and fs256s.
document number: 002-00368 rev. *j page 46 of 151 S25FS128S s25fs256s both devices also may be configured to use the sector (uniform block) erase commands to erase 256-kb logical blocks rather than individual 64-kb physical sectors. this configuration option (cr3v[ 1] = 1) allows lower density devices to emulate the same sec tor erase behavior as higher density members of the family that use 256-kb physical sectors. this can simplify software migration t o the higher density members of the family. s25fs256s sector address map, bottom 4-kb sectors, 64-kb physi cal uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 8 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa07 00007000h-00007fffh 32 1 sa08 00008000h-0000ffffh 64 511 sa09 00010000h-0001ffffh : : sa519 01ff0000h-01ffffffh s25fs256s sector address map, top 4-kb sectors, 64-kb physical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 64 511 sa00 0000000h-000ffffh sector starting address ? sector ending address :: sa510 01fe0000h-01feffffh 32 1 sa511 01ff0000h-01ff7fffh 48 sa512 01ff8000h-01ff8fffh :: sa519 01fff000h-01ffffffh s25fs256s sector address map, uniform 64-kb physical sectors sector size (kbyte) sector count sect or range address range (8-bit) notes 64 512 sa00 0000000h-000ffffh sector starting address ? sector ending address : : sa511 1ff0000h-1ffffffh s25fs256s sector address map, bottom 4-kb sectors, 256-kb logical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 8 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa07 00007000h-00007fffh 224 1 sa08 00008000h-0003ffffh 256 127 sa09 00040000h-0007ffffh : : sa135 01fc0000h-01ffffffh
document number: 002-00368 rev. *j page 47 of 151 S25FS128S s25fs256s s25fs256s sector address map, top 4-kb sectors, 256-kb logical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 256 127 sa00 0000000h-003ffffh sector starting address ? sector ending address :: sa126 01f80000h-01fbffffh 224 1 sa127 01fc0000h-01fc7fffh 48 sa128 01ff8000h-01ff8fffh :: sa135 01fff000h-01ffffffh s25fs256s sector address map, uniform 256-kb logical sectors sector size (kbyte) sector count sect or range address range (8-bit) notes 256 128 sa00 00000000h-0003ffffh sector starting address ? sector ending address : : sa127 01fc0000h-01ffffffh S25FS128S sector and memory address map, bottom 4-kb sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 8 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa07 00007000h-00007fffh 32 1 sa08 00008000h-0000ffffh 64 255 sa09 00010000h-0001ffffh : : sa263 00ff0000h-00ffffffh S25FS128S sector and memory address map, top 4-kb sectors sector size (kbyte) sector count sector range address range (byte address) notes 64 255 sa00 0000000h-000ffffh sector starting address ? sector ending address : : sa254 00fe0000h-00feffffh 32 1 sa255 00ff0000h - 00ff7fffh 4 8 sa256 00ff8000h - 00ff8fffh : : sa263 00fff000h-00ffffffh S25FS128S sector and memory address map, uniform 64-kb blocks sector size (kbyte) sector count sector range address range (byte address) notes 64 256 sa00 0000000h-0000ffffh, sector starting address ? sector ending address : : sa255 00ff0000h-0ffffffh
document number: 002-00368 rev. *j page 48 of 151 S25FS128S s25fs256s note : these are condensed tables that use a coup le of sectors as references. there are add ress ranges that are not explicitly liste d. all 4-kb sectors have the pattern xxxx000h-xxxxfffh. all 64 -kb sectors have the pattern xxx0000h-xxxffffh. all 256-kb sectors have the pattern xx00000h-xx3ffffh, xx40000h-x x7ffffh, xx80000h-xxcffffh, or xxd0000h-xxfffffh. 7.3 id-cfi address space the rdid command (9fh) reads information from a separate flas h memory address space for dev ice identification (id) and common flash interface (cfi) information. see section 11.4, device id and common flash in terface (id-cfi) address map on page 126 for the tables defining the contents of the id-cfi address space. the id-cfi address space is programmed by cypress and read-only for the host system. 7.4 jedec jesd216 serial flash disc overable parameters (sfdp) space. the rsfdp command (5ah) reads information from a separate flas h memory address space for device identification, feature, and configuration information, in accord with the jedec jesd216 st andard for serial flash discoverable parameters. the id-cfi address space is incorporated as one of the sfdp parameters. see section 11.3, serial flash discoverable parameters (sfdp) address map on page 123 for the tables defining the contents of the sf dp address space. the sfdp address space is programmed by cypress and re ad-only for the host system. S25FS128S sector address map, bottom 4-kb sectors, 256-kb logical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 8 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa07 00007000h-00007fffh 224 1 sa08 00008000h-0003ffffh 256 63 sa09 00040000h-0007ffffh : : sa71 00fc0000h-00ffffffh S25FS128S sector address map, top 4-kb sectors, 256-kb logical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 256 63 sa00 00000000h-0003ffffh sector starting address ? sector ending address :: sa62 00f80000h-00fbffffh 224 1 sa63 00fc0000h-00ff7fffh 48 sa64 00ff8000h-00ff8fffh :: sa71 00fff000h-00ffffffh S25FS128S sector and memory address map, uniform 256-kb blocks sector size (kbyte) sector count sector range address range (byte address) notes 256 64 sa00 00000000h-0003ffffh sector starting address ? sector ending address : : sa63 00fc0000h-00ffffffh
document number: 002-00368 rev. *j page 49 of 151 S25FS128S s25fs256s 7.5 otp address space each fs-s family memory device has a 1024-byte one-time prog ram (otp) address space that is separate from the main flash array. the otp area is divided into 32, individually lockable, 32-byte aligned and length regions. in the 32-byte region starting at address zero: ? the 16 lowest address bytes are programmed by cypress with a 128 -bit random number. only cypress is able to program zeros in these bytes. programming ones in these byte locations is ignored and does not affect th e value programmed by cypress. attempting to program any zero in these byte locations will fail and set p_err. ? the next 4 higher address bytes (otp lock bytes) are used to pr ovide one bit per otp region to permanently protect each region from programming. the bytes are erased wh en shipped from cypress. after an otp region is programmed, it can be locked to prevent further programming, by programming the related protection bit in the otp lock bytes. ? the next higher 12 bytes of the lowest address region are rese rved for future use (rfu). the bits in these rfu bytes may be programmed by the host system but it must be understood that a fu ture device may use those bits for protection of a larger otp space. the bytes are erased when shipped from cypress. the remaining regions are erased when shipped from cypress, a nd are available for programming of additional permanent data. refer to figure 7.1, otp address space for a pictorial representation of the otp memory space. the otp memory space is intende d for increased system security. otp values, su ch as the random number programmed by cypress, can be used to ?mate? a flash component with t he system cpu/asic to prev ent device substitution. the configuration register freeze (cr1v[0] ) bit protects the entire otp memory spac e from programming when set to 1. this allows trusted boot code to control prog ramming of otp regions then set the freeze bit to prevent further otp memory space programming during the remainder of normal power-on system operation. figure 7.1 otp address space 32-byte otp region 31 32-byte otp region 30 32-byte otp region 29 32-byte otp region 3 32-byte otp region 2 32-byte otp region 1 32-byte otp region 0 16-byte random number lock bits 31 to 0 reserved . . . region 0 expanded view when programmed to 0, each lock bit protects its related 32-byte otp region f rom any further programming ... byte 0h byte 10h byte 1fh
document number: 002-00368 rev. *j page 50 of 151 S25FS128S s25fs256s 7.6 registers registers are small groups of memory cells used to configure how the s25fs-s family memory device operates or to report the status of device operations. th e registers are accessed by specific commands. the commands (and hexadecimal instruction codes) used for each register are noted in each register description. in legacy spi memory devices the individual register bits could be a mixture of volatile, non-vol atile, or one-time programmabl e (otp) bits within the same register. in so me configuration options the type of a regi ster bit could change e.g. from non-volati le to volatile. the s25fs-s family uses separate non-volatile or volatile memo ry cell groups (areas) to implement the different register bit ty pes. however, the legacy registers and commands continue to appear and behave as they always have for legacy software compatibility. there is a non-volatile and a volatile version of each legacy regi ster when that legacy register has volatile bits or when the command to read the legacy register has zero read latency. when such a r egister is read the volatile vers ion of the register is deliver ed. during power-on reset (por), hardware reset, or software reset, the non-v olatile version of a register is copied to the volatile versi on to provide the default state of the volatile register. when non-volatile register bi ts are written the non-v olatile version of the register is erased and programmed with the new bit values and the volatile ve rsion of the register is update d with the new c ontents of the non- volatile version. when otp bits are program med the non-volatile version of the register is programmed and the appropriate bits are updated in the volatile version of the register. when volatile register bits are written, only the volatile version of the regi ster has the appropriate bits updated. the type for each bit is noted in each register description. the default state shown for each bit refers to the state after pow er-on reset, hardware reset, or softwa re reset if the bit is volatile. if the bit is non-volatile or otp, the default state is the va lue of the bit when the device is shipped from cypress. no n-volatile bits have the same cycling (erase and program) endurance as the main flas h array. otp address map region byte address range (hex) contents initial delivery state (hex) region 0 000 least significant byte of cypress programmed random number cypress programmed random number ... ... 00f most significant byte of cypress programmed random number 010 to 013 region locking bits byte 10 [bit 0] locks region 0 from programming when = 0 ... byte 13 [bit 7] locks region 31from programming when = 0 all bytes = ff 014 to 01f reserved for future use (rfu) all bytes = ff region 1 020 to 03f available for user programming all bytes = ff region 2 040 to 05f available for user programming all bytes = ff ... ... available for user programming all bytes = ff region 31 3e0 to 3ff available for user programming all bytes = ff
document number: 002-00368 rev. *j page 51 of 151 S25FS128S s25fs256s 7.6.1 status register 1 7.6.1.1 status register 1 non-volatile (sr1nv) related commands: write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h) table 7.1 register descriptions register abbreviation type bit location status register 1 sr1nv[7:0] non-volatile 7:0 status register 1 sr1v[7:0] volatile 7:0 status register 2 sr2v[7:0] volatile 7:0 configuration register 1 cr1nv[7:0] non-volatile 7:0 configuration register 1 cr1v[7:0] volatile 7:0 configuration register 2 cr2nv[7:0] non-volatile 7:0 configuration register 2 cr2v[7:0] volatile 7:0 configuration register 3 cr3nv[7:0] non-volatile 7:0 configuration register 3 cr3v[7:0] volatile 7:0 configuration register 4 cr4nv[7:0] non-volatile 7:0 configuration register 4 cr4v[7:0] volatile 7:0 ecc status register eccsr [7:0] volatile 7:0 asp register aspr[15:1] otp 15:1 asp register aspr[0] rfu 0 password register pass[63:0] non-volatile otp 63:0 ppb lock register ppbl[7:1] volatile 7:1 ppb lock register ppbl[0] volatile read only 0 ppb access register ppbar[7:0] non-volatile 7:0 dyb access register dybar[7:0] volatile 7:0 spi ddr data learning registers nvdlr[7:0] non-volatile 7:0 spi ddr data learning registers vdlr[7:0] volatile 7:0 status register 1 non-volatile (sr1nv) bits field name function type default state description 7 srwd_nv status register write disable default non-volatile 0 1 = locks state of srwd , bp, and configuration register 1 bits when wp# is low by not executing wrr or wrar commands that would affect sr1nv, sr1v, cr1nv, or cr1v. 0 = no protection, even when wp# is low. 6 p_err_d programming error default non-volatile read only 0 provides the default state for the programming error status. not user programmable. 5 e_err_d erase error default non-volatile read only 0 provides the default state for the erase error status. not user programmable. 4 bp_nv2 block protection non-volatile non-volatile 000b protects the selected range of sectors (block) from program or erase when the bp bits are configured as non-volatile (cr1nv[3]=0). programmed to 111b when bp bits are configured to volatile (cr1nv[3]=1).- after which these bits are no longer user programmable. 3 bp_nv1 2 bp_nv0
document number: 002-00368 rev. *j page 52 of 151 S25FS128S s25fs256s status register write non-volatile (srwd_nv) sr1nv[7]: places the device in the hardware protected mode when this bit is set to 1 and the wp# input is driven low. in this mode, the write registers (wrr) and write any re gister (wrar) commands (that select status register 1 or c onfiguration register 1) are ignored and not accept ed for execution, effectively locking the state of the status register 1 and configuration register 1 (sr1nv, sr1v, cr1nv , or cr1v) bits, by making the registers read-only. if wp# is high, status register 1 and configuratio n register 1 may be changed by the wrr or wrar commands. if srwd_nv is 0, wp# has no effect and status register 1 and configuration register 1 may be changed by the wrr or wrar commands. wp# has no effect on the writing of any other registers. the srwd_nv bit ha s the same non-volatile endurance as the main flash array. the srwd (sr1v[7]) bit serves only as a copy of the srwd_nv bit to provide zero read latency. program error default (p_err_d) sr1nv[6]: provides the default state for the programming error status in sr1v[6]. this bit is not user programmable. erase error (e_err) sr1v[5]: provides the default state for the erase error status in sr1v[5]. this bit is not user programmable. block protection (bp_nv2, bp_nv1, bp_nv0) sr1nv[4:2]: these bits define the main flash array area to be software-protected against program and erase commands. the bp bits are selected as either volatile or no n-volatile, depending on the state of the bp non-volatile bit (bpnv_o) in the configuration register cr1 nv[3]. when cr1nv[3] = 0 the non-volatile version of the bp bits (sr1nv[4:2]) are used to control block protection and the wrr command writes sr1nv[ 4:2] and updates sr1v[4:2] to the same value. when cr1nv[3] = 1 the volatile version of the bp bits (sr1v[4:2]) are used to contro l block protection and the wrr command writes sr1v[4:2] and does not affect sr 1nv[4:2]. when one or more of the bp bits is set to 1, the relevant memory area is protected against program and erase. the bulk erase (be) co mmand can be executed only when the bp bits are cleared to 0?s. see section 8.3, block protection on page 68 for a description of how the bp bit values select the memory array area protected. the non-volatile version of the bp bits have the same non-volatile endurance as the main flash array. write enable latch defa ult (wel_d) sr1nv[1]: provides the default state for the wel st atus in sr1v[1]. this bit is programmed by cypress and is not user programmable. write-in-progress default (wip_d) sr1nv[0]: provides the default state fo r the wip status in sr1v[0]. this bit is programmed by cypress and is not user programmable. 7.6.1.2 status register 1 volatile (sr1v) related commands: read status register (rdsr1 05h), write registers (wrr 01h) , write enable (wren 06h), write disable (wrdi 04h), clear status register (clsr 30h or 82h), read any regi ster (rdar 65h), write any regi ster (wrar 71h). this is the register displayed by the rdsr1 command. 1 wel_d wel default non-volatile read only 0 provides the default state for the wel status. not user programmable. 0 wip_d wip default non-volatile read only 0 provides the default state for the wip status. not user programmable. status register 1 non-volatile (sr1nv) bits field name function type default state description
document number: 002-00368 rev. *j page 53 of 151 S25FS128S s25fs256s status register write (srwd) sr1v[7]: srwd is a volatile copy of sr1nv[7]. this bit tracks any changes to the non-volatile version of this bit. program error (p_err) sr1v[6]: the program error bit is used as a program operation success or failure indication. when the program error bit is set to a 1 it indicates that there was an error in the last program operation. this bit will also be set w hen the user attempts to program within a protected main memory sector, or program within a locked otp region. when the program error bit is set to a 1 this bit can be cleared to 0 with the clear status regi ster (clsr) command. this is a read-only bit and is not affec ted by the wrr or wrar commands. erase error (e_err) sr1v[5]: the erase error bit is used as an erase operation success or failure indication. when the erase error bit is set to a 1 it indicates that there was an error in the last erase operation. this bit will also be set when the us er attempts to erase an individual protected main memory se ctor. the bulk erase command will not set e_err if a protected sector is found duri ng the command execution. when the erase error bit is set to a 1 this bit can be cleared to 0 with th e clear status register (clsr ) command. this is a read-only bit and is not affected by the wrr or wrar commands. block protection (bp2, bp1, bp0) sr1v[4:2]: these bits define the main flash arra y area to be software protected against program and erase commands. the bp bits are selected as either volatile or non-volatile, depending on the state of the bp non- volatile bit (bpnv_o) in the configuratio n register cr1nv[3]. when cr 1nv[3] = 0 the non-volatile version of the bp bits (sr1nv[4:2]) are used to control block protection and the wrr command writes sr1nv[ 4:2] and updates sr1v[4:2] to the same value. when cr1nv[3] = 1 the volatile version of the bp bits (sr1v[4:2]) are used to contro l block protection and the wrr command writes sr1v[4:2] and does not affect sr 1nv[4:2]. when one or more of the bp bits is set to 1, the relevant memory area is protected against program and erase. th e bulk erase (be) command can be executed only when the bp bits are cleared to 0?s. see section 8.3, block protection on page 68 for a description of how the bp bit values select the memory array area protected. status register 1 volatile (sr1v) bits field name function type default state description 7 srwd status register write disable volatile read only sr1nv volatile copy of sr1nv[7]. 6 p_err programming error occurred volatile read only 1 = error occurred. 0 = no error. 5 e_err erase error occurred volatile read only 1= error occurred. 0 = no error. 4 bp2 block protection volatile volatile protects selected range of sectors (block) from program or erase when the bp bits are configured as volatile (cr1nv[3]=1). volatile copy of sr1nv[4:2] when bp bits are configured as non-volatile. user writable when bp bits are configured as volatile. 3 bp1 2 bp0 1 wel write enable latch volatile 1 = device accepts write registers (wrr and wrar), program, or erase commands. 0 = device ignores write registers (wrr and wrar), program, or erase commands. this bit is not affected by wrr or wrar, only wren and wrdi commands affect this bit. 0 wip write-in- progress volatile read only 1= device busy, an embedded operation is in progress such as program or erase. 0 = ready device is in standby mode and can accept commands. this bit is not affected by wrr or wrar, it only provides wip status.
document number: 002-00368 rev. *j page 54 of 151 S25FS128S s25fs256s write enable latch (wel) sr1v[1]: the wel bit must be set to 1 to enable program, write, or erase operations as a means to provide protection against inadvertent changes to memory or register values. the writ e enable (wren) command execution sets the write enable latch to a 1 to allow any program, erase, or write commands to execute afte rwards. the write disable (wrdi) command can be used to set the write enable latch to a 1 to prevent all program, eras e, and write commands from execution. the wel bit is cleared to 0 at the end of any successful program, write, or erase operation. fo llowing a failed operation the wel b it may remain set and should be cleared with a wrdi command followin g a clsr command. after a power-down / power-up sequence, hardware reset, or software reset, the wr ite enable latch is set to a 0 the wrr or wrar command does not affect this bit. write-in-progress (wip) sr1v[0]: indicates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. when the bit is set to a 1 the device is busy performing an operation. while wip is 1, only read status (rdsr1 or rdsr2), read any regist er (rdar), erase suspend (ersp), program suspend (pgsp), clear status register (clsr), and software reset (reset) commands are a ccepted. ersp and pgsp will only be accepted if memory array erase or program operations are in progress. the status register e_err and p_err bits are updated while wip = 1. when p_err or e_err bits are set to 1, the wip bit will remain set to 1 indicating the device remains busy and unable to receive new operation commands. a clear status register (clsr) command must be received to return the device to standby mode. when the wip bit is cleared to 0 no op eration is in progress. this is a read-only bit. 7.6.2 status register 2 volatile (sr2v) related commands: read status register 2 (rdsr2 07h), read an y register (rdar 65h). status register 2 does not have user programmable non-volatile bits, all defined bits are volatile read only status. the default state of these bits are set by hard ware. erase status (estat) sr2v[2]: the erase status bit indicates whether the sector , selected by an immediately preceding erase status command, completed t he last erase command on that sector. the eras e status command must be issued immediately before reading sr2v to get valid erase status. reading sr2v du ring a program or erase suspend does not provide valid erase status. the erase status bit can be used by system software to detect any sector that failed its last erase operation. this can be used to detect erase operations failed due to loss of power during the erase operation. erase suspend (es) sr2v[1]: the erase suspend bit is used to determine when th e device is in erase suspend mode. this is a status bit that cannot be writt en by the user. when erase suspend bit is set to 1, the device is in erase suspend mode. when er ase suspend bit is cleared to 0, the device is not in erase suspend mode. refer to section 9.6.5, program or erase suspend (pes 85h, 75h, b0h) on page 109 for details about the erase suspend/resume commands. program suspend (ps) sr2v[0]: the program suspend bit is used to determine when the device is in program suspend mode. this is a status bit that cannot be writte n by the user. when program suspend bit is set to 1, the device is in program suspend mode. when the program suspend bit is cleared to 0, the device is not in program suspend mode. refer to section 9.6.5, program or erase suspend (pes 85 h, 75h, b0h) on page 109 for details. 7.6.3 configuration register 1 configuration register 1 controls certain interface and data prot ection functions. the register bits can be changed using the w rr command with sixteen input cycles or with the wrar command. status register 2 volatile (sr2v) bits field name function type default state description 7 rfu reserved 0 reserved for future use. 6 rfu reserved 0 reserved for future use. 5 rfu reserved 0 reserved for future use. 4 rfu reserved 0 reserved for future use. 3 rfu reserved 0 reserved for future use. 2 estat erase status volatile read only 0 1 = sector erase status command result = erase completed. 0 = sector erase status command result = erase not completed. 1 es erase suspend volatile read only 0 1 = in erase suspend mode. 0 = not in erase suspend mode. 0 ps program suspend volatile read only 0 1 = in program suspend mode. 0 = not in program suspend mode.
document number: 002-00368 rev. *j page 55 of 151 S25FS128S s25fs256s 7.6.3.1 configuration register 1 non-volatile (cr1nv) related commands: write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h). top or bottom protection (tbprot_o) cr1nv[5]: this bit defines the operation of the block protection bits bp2, bp1, and bp0 in the status register. as described in th e status register section, the bp2-0 bits allow the user to optionally protect a port ion of the array, ranging from 1/64, ?, ?, etc., up to the entire array. when tbprot_o is set to a 0 the block protection is defined to st art from the top (maximum address) of the array. when tbprot_o is set to a 1 the block prot ection is defined to start from the bott om (zero address) of the array. the tbprot_o bit is otp and set to a 0 when shipped from cypress. if tbprot_o is programmed to 1, writing the bit with a 0 does not change the value or set the program error bit (p_err in sr1v[6]). the desired state of tbprot_o must be selected during the initia l configuration of the device during system manufacture; before the first program or erase operation on the main flash array. tbpr ot_o must not be programmed af ter programming or erasing is done in the main flash array. cr1nv[4]: reserved for future use. block protection non-volatile (bpnv_o) cr1nv[3]: the bpnv_o bit defines whether the bp_nv 2-0 bits or the bp 2-0 bits in the status register are selected to contro l the block protection feature. the bpnv_o bit is otp and cleared to a 0 with the bp_ nv bits cleared to ?000? when shipped from cypress. when bpnv_o is set to a 0 the bp_nv 2-0 bits in the status register are select ed to control the block protection and are written by the wrr command. the time required to write the bp_nv bits is t w . when bpnv is set to a 1 the bp2-0 bits in the status register are sele cted to control the block protection and the bp_nv 2-0 bits will be programmed to binary ?111?. this will cause the bp 2-0 bits to be set to binary 111 after por, hardware reset, or command reset . when bpnv is set to a 1, the wrr command writes only the volatile version of the bp bits (sr1v[ 4:2]). the non-volatile version of the bp bits (sr1nv[4:2]) are no longer affected by the wrr comm and. this allows the bp bits to be written an unlimited number o f times because they are volatile and the time to write the volatile bp bits is the much faster t cs volatile register write time. if bpnv_o is programmed to 1, writing the bit with a 0 does not change the value or set the program error bit (p_err in sr1v[6]). tbparm_o cr1nv[2]: tbparm_o defines the logical location of the parameter block. the parameter block co nsists of eight 4-kb parameter sectors, which replace a 32-kb portion of the hi ghest or lowest addr ess sector. when tbparm_o is set to a 1 the parameter block is in the top of the memo ry array address space. when tbparm_o is set to a 0 the parameter block is at the bottom of the array. tbparm_o is otp and set to a 0 when it ships from cypress. if tbparm_o is programmed to 1, writing the bit with a 0 does not change the value or set the program error bit (p_err in sr1v[6]). the desired state of tbpar m_o must be selected during the in itial configuration of the device during system manu facture; before the first program or erase operation on the main flash array. t bparm_o must not be programmed after programming or erasing is done in the main flash array. tbprot_o can be set or cleared independent of the tbparm_o bit. therefore, the user can elect to store parameter information from the bottom of the array and protect boot code starting at th e top of the array, or vice vers a. or, the user can elect to s tore and protect the parameter information starti ng from the top or bottom together. configuration register 1 non-volatile (cr1nv) bits field name function type default state description 7 rfu reserved for future use non-volatile 0 reserved. 6 rfu 0 5 tbprot_o configures start of block protection otp 0 1 = bp starts at bottom (low address). 0 = bp starts at top (high address). 4 rfu reserved for future use rfu 0 reserved. 3 bpnv_o configures bp2-0 in status register otp 0 1 = volatile. 0 = non-volatile. 2 tbparm_o configures parameter sectors location otp 0 1 = 4-kb physical sectors at top, (high address). 0 = 4-kb physical sectors at bottom (low address). rfu in uniform sector configuration. 1 quad_nv quad non-volatile non-volatile 0 provides the default state for the quad bit. 0 freeze_d freeze default non-volatile read only 0 provides the default state for the freeze bit. not user programmable.
document number: 002-00368 rev. *j page 56 of 151 S25FS128S s25fs256s when the memory array is configured as uniform sectors, the t bparm_o bit is reserved for future use (rfu) and has no effect because all sectors are uniform size. quad data width non-volatile (quad_nv) cr1nv[1]: provides the default state for the q uad bit in cr1v[1]. the wrr or wrar command affects this bit. non-volatile se lection of qpi mode, by programming cr2nv[6] = 1, will also program quad_nv =1 to change the non-volatile default to quad data width mode. while qp i mode is selected by cr2v[6] = 1, the quad_nv bit cannot be cleared to 0. freeze protection defa ult (freeze) cr1nv[0]: provides the default state for the freez e bit in cr1v[0]. this bit is not user programmable. 7.6.3.2 configuration register 1 volatile (cr1v) related commands: read configuration register (rdcr 35h), writ e registers (wrr 01h), read any register (rdar 65h), write any register (wrar 71h). this is the r egister displayed by the rdcr command. tbprot, bpnv, and tbparm cr1v[5,3,2]: these bits are volatile copies of the re lated non-volatile bits of cr1nv. these bits track any changes to the related non- volatile version of these bits. quad data width (quad) cr1v[1]: when set to 1, this bit switches the data width of the device to 4-bit quad mode. that is, wp# becomes io2 and io3 / reset# beco mes an active i/o signal when cs# is low or the reset# input when cs# is high. the wp# input is not monitored for its normal function and is internally set to high (inactive). the commands for serial, and dual i/o read still function normally but, there is no need to drive the wp# input for those command s when switching between commands using different data path widths. simi larly, there is no requirement to drive the io 3 / reset# during those commands (while cs# is lo w). the quad bit must be set to 1 when using the quad i/o read, ddr quad i/o read, qpi mode (cr2v[6] = 1), and read quad id commands. while qpi mode is selected by cr2v[6] = 1, the qu ad bit cannot be cleared to 0. the wrr command writes the non- volatile version of the quad bit (cr1nv[1]) , which also causes an update to the volatile version cr1v[1]. the wrr command can not write the volatile version cr1v[1] without first affecting the non-volatile version cr1nv[1]. the wrar command must be used when it is desired to write the vola tile quad bit cr1v[1] without affect ing the non-volatile version cr1nv[1]. freeze protection (freeze) cr1v[0]: the freeze bit, when set to 1, locks the current state of the block protection control bits and otp area: ? bpnv_2-0 bits in the non-volatile status register 1 (sr1nv[4:2]) ? bp 2-0 bits in the volatile status register 1 (sr1v[4:2]) ? tbprot_o, tbparm_o, and bpnv_o bits in the non-v olatile configuration register (cr1nv[53, 2]) ? tbprot, tbparm, and bpnv bits in the volatile configuration regist er (cr1v[5, 3, 2]) are indirect ly protected in that they are shadows of the related cr1nv otp bits and are read only configuration register 1 volatile (cr1v) bits field name function type default state description 7 rfu reserved for future use volatile cr1nv reserved. 6 rfu 5 tbprot volatile copy of tbprot_o volatile read only not user writable. see cr1nv[5] tbprot_o. 4 rfu reserved for future use rfu reserved. 3 bpnv volatile copy of bpnv_o volatile read only not user writable. see cr1nv[3] bpnv_o. 2 tbparm volatile copy of tbparm_o volatile read only not user writable. see cr1nv[2] tbparm_o. 1 quad quad i/o mode volatile 1 = quad. 0 = dual or serial. 0 freeze lock-down block protection until next power cycle volatile lock current state of block protection control bits, and otp regions. 1 = block protection and otp locked. 0 = block protection and otp unlocked.
document number: 002-00368 rev. *j page 57 of 151 S25FS128S s25fs256s ? the entire otp memory space any attempt to change the above listed bits while freeze = 1 is prevented: ? the wrr command does not affect the list ed bits and no error status is set. ? the wrar command does not affect the list ed bits and no error status is set. ? the otpp command, with an address within the otp area, fails and the p-err status is set. as long as the freeze bit remains cleared to logic 0 the blo ck protection control bits and freeze are writable, and the otp address space is programmable. once the freeze bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power-on cycle or a har dware reset. software reset will not af fect the state of the freeze bit. the cr1v[0] freeze bit is volatile and the default state of freeze after power-o n comes from freeze_d in cr1nv[0]. the freeze bit can be set in parallel with updating other values in cr1v by a single wrr or wrar command. the freeze bit does not prevent the wrr or wrar co mmands from changing the srwd_nv (sr1nv[7]), quad_nv (cr1nv[1]), or quad (cr1v[1]) bits. 7.6.4 configuration register 2 configuration register 2 controls certain interface functions. the register bits can be read and changed using the read any reg ister and write any register commands. the non-vola tile version of the register provides th e ability to set the por, hardware reset, or software reset state of the controls. these configuration bits are otp and may only have their default state changed to the opp osite value one time during system configuration. the volatile versi on of the register controls the feature behavior during normal operation. 7.6.4.1 configuration register 2 non-volatile (cr2nv) related commands: read any register (rda r 65h), write any register (wrar 71h). address length non-volatile cr2nv[7]: this bit controls the por, hardware rese t, or software reset state of the expected address length for all commands that require address and are not fixe d 3-byte only or 4-byte (32-bit) only address. most comman ds that need an address are legacy spi commands t hat traditionally used 3-byte (24-bit) address. for device densities greater than 128 mbit a 4-byte address is required to access the entire memory array. the address length configuration bit is used to change most 3-byte address commands to expect 4-byte address. see s25fs-s family command set (sorted by function) on page 79 for command address length. the use of 4-byte addr ess length also applies to the 128-mbit member of the s25fs-s family so that the same 4-byte address hardware and software interface may be used fo r all family members to simplify migration between densities. the 128-mbit member of the s25fs-s family simply ignores the co ntent of the fourth, high order, address byte. this non-volatile configuration register 2 non-volatile (cr2nv) bits field name function type default state description 7 al_nv address length otp 0 1 = 4-byte address. 0 = 3-byte address. 6 qa_nv qpi 0 1 = enabled - qpi (4-4-4) protocol in use. 0 = disabled - legacy spi protocols in use, instruction is always serial on si. 5 io3r_nv io3 reset 0 1 = enabled - io3 is used as reset# input when cs# is high or quad mode is disabled cr1v[1]=1. 0 = disabled - io3 has no alternate function, hardware reset is disabled. 4 rfu reserved 0 reserved for future use. 3 rl_nv read latency 1 0 to 15 latency (dummy) cycles following read address or continuous mode bits. note that bit 3 has a default value of 1 and may be programmed one time to 0 but cannot be returned to 1. 2 0 1 0 0 0
document number: 002-00368 rev. *j page 58 of 151 S25FS128S s25fs256s address length configuration bit enables the device to start i mmediately (boot) in 4-byte address mode rather than the legacy 3 -byte address mode. qpi non-volatile cr2nv[6]: this bit controls the por, hardwa re reset, or software reset state of the expected instruction width for all commands. legacy spi commands always send the instruction o ne bit wide (serial i/o) on the si (io0) signal. the s25fs-s family also supports the qpi mode in which all transfers betwe en the host system and memory are 4-bits wide on io0 to io3, including all instructions. this non-volatile qpi configuration bi t enables the device to start immediately (boot) in qpi mode rather than the legacy serial instruction mode. when this bit is progra mmed to qpi mode, the quad_nv bit is also programmed to quad mode (cr1nv[1] = 1). the recommended procedure for moving to qpi mode is to first use the wrar command to set cr2v[6] = 1, qpi mode. the volatile register write for qpi mode has a short and well defined time (t cs ) to switch the device interface into qpi mode. following commands can then be immediately sent in qpi protocol. the wrar command can be used to program cr2nv[6] = 1, followed by polling of sr1v[0] to know when the prog ramming operation is completed. similarly, to exit qpi mode, the wrar command is used to clear cr2v[6] = 0. cr2 nv[6] cannot be erased to 0 because it is otp. io3 reset non-volatile cr2nv[5]: this bit controls the por, hardware reset, or software reset state of the io3 signal behavior. most legacy spi devices do not have a hardware reset input signal due to the limited signal count and connections available in traditional spi device packages. the s25fs-s family provides the option to use the io3 signal as a hardware reset input when th e io3 signal is not in use for transferring information between the host system and the memory. this non-volatile io3 reset configuration bit enables the device to start immediately (boot) with io3 enabled for use as a reset# signal. read latency non-volatile cr2nv[3:0]: this bit controls the por, hardware rese t, or software reset state of the read latency (dummy cycle) delay in all variable latency read commands. t he following read commands have a variable latency period between the end of address or mode and the beginning of read data returning to the host: ? fast read ? dual i/o read ? quad i/o read ? ddr quad i/o read ? otpr ? eccrd ? rdar this non-volatile read latency configuration bit sets the number of read latency (dummy cycles) in use so the device can start immediately (boot) with an appropriate read latency for the host system. latency code (cycles) versus frequency latency cycles read command maximum frequency (mhz) fast read (1-1-1) otpr (1-1-1) rdar (1-1-1) rdar (4-4-4) dual i/o (1-2-2) quad i/o (1-4-4) qpi (4-4-4) ddr quad i/o (1-4-4) ddr qpi (4-4-4) (note 4) mode cycles = 0 mode cycles = 4 mode cycles = 2 mode cycles = 1 050 80 40 n/a 166925322 2 80 104 66 34 3 92 116 80 45 4 104 129 92 57 5 116 133 104 68 6 129 133 116 80 7 133 133 129 80 8 133 133 133 80 9 133 133 133 80 10 133 133 133 80 11 133 133 133 80
document number: 002-00368 rev. *j page 59 of 151 S25FS128S s25fs256s notes: 1. sck frequency > 133 mhz sdr, or > 80 mhz ddr is not supported by this family of devices. 2. the dual i/o, quad i/o, qpi, ddr quad i/o, and ddr qpi, command protocols include continuous read mode bits following the add ress. the clock cycles for these bits are not counted as part of the latency cycl es shown in the table. example: the legacy quad i/o command has 2 continuous read mode cycles following the address. therefore, the legacy quad i/o command without additio nal read latency is supported only up to the frequency shown in the table for a read latency of 0 cycles. by increasing the variable read latency the frequen cy of the quad i/o command can be increased to allow operation up to the maximum supported 133 mhz frequency. 3. other read commands have fixed latency, e.g. read always ha s zero read latency. rsfdp always has eight cycles of latency. 4. ddr qpi is only supported for latency cycles 1 through 5 and for clock frequency of up to 68 mhz. 7.6.4.2 configuration register 2 volatile (cr2v) related commands: read any register (rdar 65h ), write any register (wrar 71h), 4bam. address length cr2v[7]: this bit controls the expected address length for al l commands that require address and are not fixed 3- byte only or 4-byte (32-bit) only address. see s25fs-s family command set (sorted by function) on page 79 for command address length. this volatile address length conf iguration bit enables the address length to be changed during normal operation. the 4- byte address mode (4bam) command directly sets this bit into 4-byte address mode. qpi cr2v[6]: this bit controls the expected instru ction width for all commands. this volatile qpi configuration bit enables the device to enter and exit qpi mode during normal operation. when th is bit is set to qpi mode, the quad bit is also set to quad m ode (cr1v[1] = 1). when this bit is cleared to legacy spi mode, the quad bit is not affected. io3 reset cr2v[5]: this bit controls the io3 / reset# signal behavior. this volatile io3 reset configuration bit enables the use of io3 as a reset# input dur ing normal operation. 12 133 133 133 80 13 133 133 133 80 14 133 133 133 80 15 133 133 133 80 configuration register 2 volatile (cr2v) bits field name function type default state description 7 al address length volatile cr2nv 1 = 4 byte address. 0 = 3 byte address. 6 qa qpi 1 = enabled - qpi (4-4-4) protocol in use. 0 = disabled - legacy spi protocols in use, instruction is always serial on si. 5 io3r_s io3 reset 1 = enabled - io3 is used as reset# input when cs# is high or quad mode is disabled cr1v[1]=1. 0 = disabled - io3 has no alternate function, hardware reset is disabled. 4 rfu reserved reserved for future use. 3 rl read latency 0 to 15 latency (dummy) cycles following read address or continuous mode bits. 2 1 0 latency code (cycles) versus frequency latency cycles read command maximum frequency (mhz) fast read (1-1-1) otpr (1-1-1) rdar (1-1-1) rdar (4-4-4) dual i/o (1-2-2) quad i/o (1-4-4) qpi (4-4-4) ddr quad i/o (1-4-4) ddr qpi (4-4-4) (note 4) mode cycles = 0 mode cycles = 4 mode cycles = 2 mode cycles = 1
document number: 002-00368 rev. *j page 60 of 151 S25FS128S s25fs256s read latency cr2v[3:0]: this bit controls the read latency (dummy cycle) delay in variable latency read commands these volatile configuration bits enable the user to adjust the read latency during normal operation to optimiz e the latency for different com mands or, at different operating frequencies, as needed. 7.6.5 configuration register 3 configuration register 3 controls certain command behaviors. t he register bits can be read and changed using the read any register and write any register commands. t he non-volatile register provides the por, hardware reset, or software reset state o f the controls. these confi guration bits are otp and may be programmed to thei r opposite state one time during system configurati on if needed. the volatile version of configur ation register 3 allows the configuration to be changed during system operation or t esting. 7.6.5.1 configuration register 3 non-volatile (cr3nv) related commands: read any register (rda r 65h), write any register (wrar 71h). blank check non-volatile cr3nv[5]: this bit controls the por, ha rdware reset, or software reset state of the blank check during erase feature. 02h non-volatile cr3nv[4]: this bit controls the por, hard ware reset, or software reset state of the page programming buffer address wrap point. 20h non-volatile cr3nv[3]: this bit controls the por, hardware reset, or softwa re reset state of the availability of 4-kb parameter sectors in the main flash array address map. 30h non-volatile cr3nv[2]: this bit controls the por, hardwa re reset, or software reset state of the 30h instruction code is used. d8h non-volatile cr3nv[1]: this bit controls the por, hardwa re reset, or software reset state of the configuration for the size of the area erased by the d8 h or dch instructions. f0h non-volatile cr3nv[0]: this bit controls the por, hardware reset, or soft ware reset state of the availability of the cypress legacy fl-s family softwa re reset instruction. 7.6.5.2 configuration register 3 volatile (cr3v) related commands: read any register (rda r 65h), write any register (wrar 71h). configuration register 3 non-volatile (cr3nv) bits field name function type default state description 7 rfu reserved otp 0 reserved for future use. 6 rfu reserved 0 reserved for future use. 5 bc_nv blank check 0 1 = blank check during erase enabled. 0 = blank check disabled. 4 02h_nv page buffer wrap 0 1 = wrap at 512 bytes. 0 = wrap at 256 bytes. 3 20h_nv 4-kb erase 0 1 = 4-kb erase disabled (uniform sector architecture). 0 = 4-kb erase enabled (hybrid sector architecture). 2 30h_nv clear status / resume select 0 1 = 30h is erase or program resume command. 0 = 30h is clear status command. 1 d8h_nv block erase size 0 1 = 256-kb erase. 0 = 64-kb erase. 0 f0h_nv legacy software reset enable 0 1 = f0h software reset is enabled. 0 = f0h software reset is disabled (ignored).
document number: 002-00368 rev. *j page 61 of 151 S25FS128S s25fs256s blank check volatile cr3v[5]: this bit controls the blank check during erase fe ature. when this featur e is enabled an erase command first evaluates the erase status of the sector. if the sector is found to have not completed its la st erase successfull y, the sector is unconditionally erased. if the la st erase was successful, the sector is read to determine if the sector is still eras ed (blank). the erase operation is started immediately after finding any programmed zero. if the sect or is already blank (no programmed zer o bit found) the remainder of the erase operation is skipped. this can dramatically reduce erase time when sectors being erased d o not need the erase operation. when enabled th e blank check feature is used within the pa rameter erase, sector erase, and bulk erase commands. when blank check is disabled an erase command unconditionally starts the erase operation. 02h volatile cr3v[4]: this bit controls the page programming buffer addre ss wrap point. legacy spi devices generally have used a 256-byte page programming buffer and defin ed that if data is loaded into the buffer beyond the 255-byte location, the address at which additional bytes are loaded would be wrapped to address zero of the buffer. the s25fs-s family provides a 512-byte page programming buffer that can increase progr amming performance. for legacy software compatibility, this configuration bit provide s the option to continue the wrapping behavior at the 256-byte boundary or to enable full use of the available 512-byte buffer by not wrapping the load address at the 256-byte boundary. 20h volatile cr3v[3]: this bit controls the availability of 4-kb paramet er sectors in the main flash array address map. the parameter sectors can overlay the highest or lowest 32-kb addre ss range of the device or they can be removed from the address map so that all sectors are uniform size. this bit shall not be written to a value different than the value of cr3nv[3]. the va lue of cr3v[3] may only be changed by writing cr3nv[3]. 30h volatile cr3v[2]: this bit controls how the 30h instruction code is used. the instruction may be used as a clear status command or as an alternate program / erase resume command. th is allows software compatibilit y with either cypress legacy spi devices or alternate vendor devices. d8h volatile cr3v[1]: this bit controls the area erased by the d8h or dch instructions. the in struction can be used to erase 64-kb physical sectors or 256-kb size and aligned blocks. the option to erase 256-kb blocks in the lower density family members allow s for consistent software behavior across all densities that can ease migration between different densities. f0h volatile cr3v[0]: this bit controls the availability of the cypress lega cy fl-s family software rese t instruction. the s25fs-s family supports the industry common 66h + 99h instruction sequenc e for software reset. this configuration bit allows the option to continue use of the legacy f0h single command for software reset. 7.6.6 configuration register 4 configuration register 4 controls the main flash array read co mmands burst wrap behavior. the burst wrap config uration does not affect commands reading from areas other than the main flas h array e.g. read commands for registers or otp array. the non- volatile version of the register provides the ability to set the start up (boot) stat e of the controls as the contents are copi ed to the volatile version of the register during the por, hardware reset, or software reset. th e volatile version of the register contro ls the feature behavior during normal operation. the register bits can be read and changed using the read any register and write any register commands. the volatile version of the register can also be written by the set burst length (c0h) command. configuration register 3 volatile (cr3v) bits field name function type default state description 7 rfu reserved volatile cr3nv reserved for future use. 6 rfu reserved reserved for future use. 5 bc_v blank check 1 = blank check during erase enabled. 0 = blank check disabled. 4 02h_v page buffer wrap 1 = wrap at 512 bytes. 0 = wrap at 256 bytes. 3 20h_v 4-kb erase volatile, read only 1 = 4-kb erase disabled (uniform sector architecture). 0 = 4-kb erase enabled (hybrid sector architecture). 2 30h_v clear status / resume select volatile 1 = 30h is erase or program resume command. 0 = 30h is clear status command. 1 d8h_v block erase size 1 = 256-kb erase. 0 = 64-kb erase. 0 f0h_v legacy software reset enable 1 = f0h software reset is enabled. 0 = f0h software reset is disabled (ignored).
document number: 002-00368 rev. *j page 62 of 151 S25FS128S s25fs256s 7.6.6.1 configuration register 4 non-volatile (cr4nv) related commands: read any register (rda r 65h), write any register (wrar 71h). output impedance non- volatile cr4nv[7:5]: these bits control the por, hardware rese t, or software reset state of the io signal output impedance (drive strength) . multiple drive strength are available to help match the output impedance with the system pri nted circuit board environment to minimize overshoot and ringing. t hese non-volatile output impedance configuration bits enable the device to start immediately (boot) with the appropriate drive strength. wrap enable non-volatile cr4nv[4]: this bit controls the por, hardware reset, or software reset state of the wrap enable. the commands affected by wrap enable are: quad i/o read, and ddr quad i/o read. this conf iguration bit enables the device to start immediately (boot) in wrapped burst read mo de rather than the legacy sequential read mode. wrap length non-vo latile cr4nv[1:0]: these bits controls the por, hardware rese t, or software reset state of the wrapped read length and alignment. these non-volatile co nfiguration bits enable the device to st art immediately (boot) in wrapped burst read mode rather than the legacy sequential read mode. 7.6.6.2 configuration register 4 volatile (cr4v) related commands: read any register (rdar 65h), write any register (wrar 71h), set burst length (sbl c0h). configuration register 4 non-volatile (cr4nv) bits field name function type default state description 7 oi_o output impedance otp 0 see output impedance control . 6 0 5 0 4 we_o wrap enable 1 0 = wrap enabled. 1 = wrap disabled. 3 rfu reserved 0 reserved for future use. 2 rfu reserved 0 reserved for future use. 1 wl_o wrap length 0 00 = 8-byte wrap. 01 = 16-byte wrap. 10 = 32-byte wrap. 11 = 64-byte wrap. 0 0 output impedance control cr4nv[7:5] impedance selection typical impedance to v ss (ohms) typical impedance to v cc (ohms) notes 000 47 45 factory default 001 124 105 010 71 64 011 47 45 100 34 35 101 26 28 110 22 24 111 18 21
document number: 002-00368 rev. *j page 63 of 151 S25FS128S s25fs256s output impedance cr2v[7:5]: these bits control the io signa l output impedance (drive strength). this volatile output impedance configuration bit enables the user to adjust the drive strength during normal operation. wrap enable cr4v[4]: this bit controls the burst wrap fe ature. this volatile configuration bi t enables the device to enter and exit burst wrapped read mode during normal operation. wrap length cr4v[1:0]: these bits controls the wrapped read length and alignment during normal operation. these volatile configuration bits enable the user to adjust th e burst wrapped read length during normal operation. 7.6.7 ecc status register (eccsr) related commands: ecc read (eccrd 18h or 19h). eccsr does no t have user programmable non-volatile bits, all defined bits are volatile read only status. the default st ate of these bits are set by hardware. the status of ecc in each ecc unit is provided by the 8-bit ecc status register (eccsr). th e ecc register read command is written followed by an ecc unit address. the contents of the st atus register then indicates, for the selected ecc unit, whether there is an error in the ecc, the ecc unit data, or that ecc is disabled for that ecc unit. eccsr[2] = 1 indicates an error was corrected in the ecc. eccsr[ 1] = 1 indicates an error was corrected in the ecc unit data. eccsr[0] = 1 indicates the ecc is disabled. the default state of ?0? for all these bits indicates no failures and ecc is enable d. the eccsr[7:3] are reserv ed. these have undefined high or low values that can change from one ecc status read to another. these bits should be treated as ?don?t care? and ignored by any software reading status. 7.6.8 asp register (aspr) related commands: asp read (asprd 2bh) and asp program (aspp 2f h), read any register (rdar 65h), write any register (wrar 71h). the asp register is a 16-bit otp memory lo cation used to permanen tly configure the behavior of ad vanced sector protection (asp) features. aspr does not have us er programmable volatile bi ts, all defined bits are otp. configuration register 4 volatile (cr4v) bits field name function type default state description 7 oi output impedance volatile cr4nv see output impedance control on page 62 . 6 5 4 we wrap enable 0 = wrap enabled. 1 = wrap disabled. 3 rfu reserved reserved for future use. 2 rfu reserved reserved for future use. 1 wl wrap length 00 = 8-byte wrap. 01 = 16-byte wrap. 10 = 32-byte wrap. 11 = 64-byte wrap. 0 ecc status register (eccsr) bits field name function type default state description 7 to 3 rfu reserved 0 reserved for future use 2 eecc error in ecc volatile, read only 0 1 = single bit error found in the ecc unit error correction code 0 = no error. 1 eeccd error in ecc unit data volatile, read only 0 1 = single bit error corrected in ecc unit data. 0 = no error. 0 eccdi ecc disabled volatile, read only 0 1 = ecc is disabled in the selected ecc unit. 0 = ecc is enabled in the selected ecc unit.
document number: 002-00368 rev. *j page 64 of 151 S25FS128S s25fs256s the default state of the aspr bi ts are programmed by cypress. password protection mode lock bit (pwdmlb) aspr[2]: when programmed to 0, the password protection mode is permanently selected. persistent protection mode lock bit (pst mlb) aspr[1]: when programmed to 0, the persistent protection mode is permanently selected. pwdmlb (aspr[2]) and pstmlb (aspr[1]) are mutually exclusive, only one may be programmed to 0. aspr bits may only be programmed while aspr[2:1] = 11b. attempting to program aspr bits when aspr[2:1] is not = 11b will result in a programming error with p_err (sr1v[6]) set to 1. after the asp protection mo de is selected by programming aspr[2:1] = 10b or 01b, the state of all aspr bits are locked and permanent ly protected from further programming. attempting to program aspr[2:1] = 00b will result in a prog ramming error with p_err (sr1v[6]) set to 1. similarly, otp configuration bits lis ted in the asp register description ( see asp register on page 72. ), may only be programmed while aspr[2:1] = 11b. the otp configuration must be selected bef ore selecting the asp protection mode. the otp configuration bits are permanently protected from further change when the asp protection mode is selected. attempting to program these otp configuration bits when aspr[2:1] is not = 11b will result in a pr ogramming error with p_err (sr1v[6]) set to 1. the asp protection mode should be selected dur ing system configuration to ensure that a malicious program does not select an undesired protection mode at a later time. by locking all the protection configuration via the asp mode selection, later altera tion of the protection methods by malicious programs is prevented. 7.6.9 password register (pass) related commands: password re ad (passrd e7h) and password program (passp e 8h), read any register (rdar 65h), write any register (wrar 71h). the pass register is a 64-bit otp memory location used to permanently define a password for the advanced sector protection (asp) feature. pass does not have user programmable volatile bi ts, all defined bits are otp. a volat ile copy of pass is used to satisfy read latency requirements but t he volatile register is not user writable or further described. asp register (aspr) bits field name function type default state description 15 to 9 rfu reserved otp 1 reserved for future use. 8 rfu reserved otp 1 reserved for future use. 7 rfu reserved otp 1 reserved for future use. 6 rfu reserved otp 1 reserved for future use. 5 rfu reserved otp 1 reserved for future use. 4 rfu reserved rfu 1 reserved for future use. 3 rfu reserved rfu 1 reserved for future use. 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mode permanently enabled. 1 = password protection mode not permanently enabled. 1 pstmlb persistent protection mode lock bit otp 1 0 = persistent protection mode permanently enabled. 1 = persistent protection mode not permanently enabled. 0 rfu reserved rfu 1 reserved for future use. password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff- ffffffffh non-volatile otp storage of 64-bit password. the password is no longer readable after the password protection mode is selected by programming asp register bit 2 to 0.
document number: 002-00368 rev. *j page 65 of 151 S25FS128S s25fs256s 7.6.10 ppb lock register (ppbl) related commands: ppb lock read (plbrd a7h, plbwr a6h), read any register (rdar 65h). ppbl does not have separa te user programmable non -volatile bits, all defined bits are volatile read only status. the default st ate of the rfu bits is set by hardware. the defau lt state of the ppblock bit is defined by the asp protection mode bits in aspr[2:1]. there is no non-volatile version of the ppbl register. the ppblock bit is used to protect the ppb bits. w hen ppbl[0] = 0, the ppb bits can not be programmed. 7.6.11 ppb access register (ppbar) related commands: ppb read (ppbrd fch or 4ppbrd e2h), ppb program (ppbp fdh or 4ppbp e3h), ppb erase (ppbe e4h). ppbar does not have user writable volatile bits, all ppb array bits ar e non-volatile. the def ault state of the ppb array is era sed to ffh by cypress. there is no vola tile version of the ppbar register. 7.6.12 dyb access register (dybar) related commands: dyb read (dybrd fah or 4dybrd e0h) and dyb write (dybwr fbh or 4dybwr e1h). dybar does not have user programmable non-vol atile bits, all bits are a r epresentation of the volatile bits in the dyb array. t he default state of the dyb array bits is set by hardware. there is no non-vo latile version of the dybar register. 7.6.13 spi ddr data learning registers related commands: program nvdlr (pnvdlr 43h), write vdlr (wvdlr 4ah), data learning pattern read (dlprd 41h), read any register (rdar 65h), write any register (wrar 71h). the data learning pattern (dlp) resides in an 8-bit non-volatile da ta learning register (nvdlr) as well as an 8-bit volatile da ta learning register (vdlr). when shipped from cypress, the nvdlr value is 00h. once programmed, the nvdlr cannot be reprogrammed or erased; a copy of the data pattern in the nvdlr wil l also be written to the vdlr. the vdlr can be written to at any time, but on reset or power cycles the data pattern will revert back to what is in the nvdl r. during the learning phase des cribed in the spi ddr modes, the dlp will come from the vdlr. each io will output the same dlp value for every clock edge. for ppb lock register (ppbl) bits field name function type default state description 7 to 1 rfu reserved volatile 00h reserved for future use 0 ppblock protect ppb array volatile read only aspr[2:1] = 1xb = persistent protection mode = 1 aspr[2:1] = 01b = password protection mode = 0 0 = ppb array protected. 1 = ppb array may be programmed or erased. ppb access register (ppbar) bits field name function type default state description 7 to 0 ppb read or program per sector ppb non-volatile ffh 00h = ppb for the sector addressed by the ppbrd or ppbp command is programmed to 0, protecting that sector from program or erase operations. ffh = ppb for the sector addressed by the ppbrd command is 1, not protecting that sector from program or erase operations. dyb access register (dybar) bits field name function type default state description 7 to 0 dyb read or write per sector dyb volatile ffh 00h = dyb for the sector addressed by the dybrd or dybwr command is cleared to 0, protecting that sector from program or erase operations. ffh = dyb for the sector addressed by the dybrd or dybwr command is set to 1, not protecting that sector from program or erase operations.
document number: 002-00368 rev. *j page 66 of 151 S25FS128S s25fs256s example, if the dlp is 34h (or binary 00110100) then during th e first clock edge all io?s will output 0; subsequently, the 2nd clock edge all i/o?s will output 0, the 3rd will output 1, etc. when the vdlr value is 00h, no preamb le data pattern is presented durin g the dummy phase in the ddr commands. non-volatile data lear ning register (nvdlr) bits field name function type default state description 7 to 0 nvdlp non-volatile data learning pattern otp 00h otp value that may be transferred to the host during ddr read command latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. volatile data learning register (vdlr) bits field name function type default state description 7 to 0 vdlp volatile data learning pattern volatile takes the value of nvdlr during por or reset volatile copy of the nvdlp used to enable and deliver the data learning pattern (dlp) to the outputs. the vdlp may be changed by the host during system operation.
document number: 002-00368 rev. *j page 67 of 151 S25FS128S s25fs256s 8. data protection 8.1 secure silicon region (otp) the device has a 1024 byte one-time program (otp) address space th at is separate from the main flash array. the otp area is divided into 32, individually lockable, 32-byte aligned and length regions. the otp memory space is intended for increased system security . otp values can ?mate? a flash component with the system cpu/asic to prevent device substitution. see otp address space on page 49 , otp program (otpp 42h) on page 111 , and otp read (otpr 4bh) on page 112 . 8.1.1 reading otp memory space the otp read command uses the same protocol as fast read. otp read operations outside the valid 1-kb otp address range will yield indeterminate data. 8.1.2 programming otp memory space the protocol of the otp programming command is the same as page program. the otp program command can be issued multiple times to any given otp address, but this address space can never be erased. automatic ecc is programmed on the first programming operation to each 16 byte region. programming within a 16 byte region more than once disables the ecc. it is recommended to program each 16 byte portion of each 32 byte region once so that ecc remains enabled to provide the best data integrity. the valid address range for otp program is depicted in figure 7.1, otp address space on page 49 . otp program operations outside the valid otp address range will be ignored, without p_err in sr1v set to 1. otp program operations within the valid ot p address range, while freeze = 1, will fail with p_err in sr1v set to 1. the otp address space is not protected by the selection of an asp protection mode. the fr eeze bit (cr1v[0]) may be used to protect the otp address space. 8.1.3 cypress programmed random number cypress standard practice is to program the low order 16 bytes of the otp memory space (locations 0x0 to 0xf) with a 128-bit random number using the linear congruential random number meth od. the seed value for the algorithm is a random number concatenated with the day and time of tester insertion. 8.1.4 lock bytes the lsb of each lock byte protects the lowest address region related to the byte, the msb protects the highest address region related to the byte. the next higher address byte similarly prot ects the next higher 8 regions. the lsb bit of the lowest addre ss lock byte protects the higher address 16 bytes of the lowest address region. in other word s, the lsb of location 0x10 protects all t he lock bytes and rfu bytes in the lowest address region from further programming. see otp address space on page 49.
document number: 002-00368 rev. *j page 68 of 151 S25FS128S s25fs256s 8.2 write enable command the write enable (wren) command must be written prior to an y command that modifies non-volatile data. the wren command sets the write enable latch (wel) bit. the wel bit is cleared to 0 (disables writes) during power-u p, hardware reset, or after the device completes t he following commands: reset page program (pp or 4pp) parameter 4-kb erase (p4e or 4p4e) sector erase (se or 4se) bulk erase (be) write disable (wrdi) write registers (wrr) write any register (wrar) otp byte programming (otpp) advanced sector protection register program (aspp) persistent protection bit program (ppbp) persistent protection bit erase (ppbe) password program (passp) program non-volatile data learning register (pnvdlr) 8.3 block protection the block protect bits (status register bits bp2, bp1, bp0) in combination with the configuratio n register tbprot_o bit can be used to protect an address range of the main flash array from program and erase operations. the size of the range is determined by the value of the bp bits and the upper or lower starting point of the range is selected by the tb prot_o bit of the configuratio n register (cr1nv[5]). upper array start of protection (tbprot_o = 0) status register content protected fraction of memory array protected memory (kbytes) bp2 bp1 bp0 fs128s 128 mb fs256s 256 mb 0 0 0 none 0 0 0 0 1 upper 64th 256 512 0 1 0 upper 32nd 512 1024 0 1 1 upper 16th 1024 2048 1 0 0 upper 8th 2048 4096 1 0 1 upper 4th 4096 8192 1 1 0 upper half 8192 16384 1 1 1 all sectors 16384 32768
document number: 002-00368 rev. *j page 69 of 151 S25FS128S s25fs256s when block protection is enabled (i.e., any bp2-0 are set to 1), advanced sector protection (asp) can still be used to protect sectors not protected by the block protecti on scheme. in the case that both asp and bl ock protection are used on the same secto r the logical or of asp and block protecti on related to the sector is used. 8.3.1 freeze bit bit 0 of configuration r egister 1 (cr1v[0]) is the freeze bit. the freeze bi t, when set to 1, locks the current state of the blo ck protection control bits and otp area until the ne xt power off-on cycle. additional details in configuration register 1 volatile (cr1v) on page 56 . 8.3.2 write protect signal the write protect (wp#) input in combinati on with the status regi ster write disable (srwd) bit (s r1nv[7]) provide hardware inpu t signal controlled protection. when wp# is low and srwd is set to 1 status register 1 (sr1nv and sr1v) and configuration register 1 (cr1nv and cr1v) are pr otected from alteration. this pr events disabling or changing the protection defined by the bl ock protect bits. see status register 1 on page 51 . 8.4 advanced sector protection advanced sector protection (asp) is the name used for a set of independent hardware and softwar e methods used to disable or enable programming or erase operations, individually, in any or all sectors. every main flash array sector has a non-volatile persistent pr otection bit (ppb) and a volatile dynamic protection bit (dyb) associated with it. when either bit is 0, the sector is protec ted from program and erase operati ons. the ppb bits are protected from program and erase when the volatile ppb lock bit is 0. there are two methods for managing the state of the ppb lock bit: password protection and persistent protection. an overview of these methods is shown in figure 8.2, advanced sector protection overview on page 71 . block protection and asp protection settings for each sector are logically ored to defin e the protection for each sector i.e. i f either mechanism is protecting a sector the sector cannot be programmed or erased. refer to block protection on page 68 for full details of the bp2-0 bits. lower array start of protection (tbprot_o = 1) status register content protected fraction of memory array protected memory (kbytes) bp2 bp1 bp0 fs128s 128 mb fs256s 256 mb 0 0 0 none 0 0 0 0 1 lower 64th 256 512 0 1 0 lower 32nd 512 1024 0 1 1 lower 16th 1024 2048 1 0 0 lower 8th 2048 4096 1 0 1 lower 4th 4096 8192 1 1 0 lower half 8192 16384 1 1 1 all sectors 16384 32768
document number: 002-00368 rev. *j page 70 of 151 S25FS128S s25fs256s figure 8.1 sector protection control sector 0 logical or sector 0 sector 0 block sector 1 logical or sector 1 sector 1 sector n logical or sector n sector n ... ... ... ... protection logic persistent protection bits array (ppb) dynamic protection bits array (dyb) flash memory array
document number: 002-00368 rev. *j page 71 of 151 S25FS128S s25fs256s figure 8.2 advanced sector protection overview the persistent protection method sets the ppb lock bit to 1 durin g por, or hardware reset so t hat the ppb bits are unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb. there is no comman d in the persistent protection method to set the ppb lock bit to 1, therefore the ppb lock bit will rema in at 0 until the next power-off or hardwar e reset. the persistent protection method allows boot code the option of changing sector prot ection by programming or erasing the ppb, then protecting the ppb from furt her change for the remainder of normal system operation by clea ring the ppb lock bit to 0. thi s is sometimes called boot-code controlled sector protection. power on / reset aspr[2]=0 aspr[1]=0 ppblock = 0 ppb bits locked ppblock = 1 ppb bits erasable aspr bits locked aspr bits locked aspr bits are programmable and programmable password unlock ppblock = 1 ppb bits erasable and programmable password protection persistent protection default persistent protection ppb lock bit write ppb lock bit write ppblock = 0 ppb bits locked yes yes yes yes yes no no no no no password protection mode protects the persistent protection mode does not default mode allows protect the ppb after power up. the bits may be changed. a ppb lock bit write command protects the ppb bits until the next power-off or reset. ppb after power up. a password unlock command will enable changes to ppb. a ppb lock bit write command turns protection back on. aspr to be programmed to permanently select the protection mode. the default mode otherwise acts the same as the persistent protection mode. after one of the protection modes is selected, aspr is no longer programmable, making the selected protection mode permanent.
document number: 002-00368 rev. *j page 72 of 151 S25FS128S s25fs256s the password method clears the ppb lock bit to 0 during por, or hardware reset to pr otect the ppb. a 64-bit password may be permanently programmed and hidden for the password method. a comm and can be used to provide a password for comparison with the hidden password. if the passw ord matches, the ppb lock bit is set to 1 to u nprotect the ppb. a command can be used to clear the ppb lock bit to 0. this method requires use of a password to control ppb protection. the selection of the ppb lock bit management method is made by programming otp bits in the asp register so as to permanently select the method used. 8.4.1 asp register the asp register is used to permanently configure the behavior of advanc ed sector protection (asp) features. see asp register (aspr) on page 64 . as shipped from the factory, all devices default asp to the persistent protection mo de, with all sectors u nprotected, when powe r is applied. the device programmer or host system must then choose which sector protection method to use. programming either of the, one-time programmable, protec tion mode lock bits, locks the part permanently in t he selected mode: ? aspr[2:1] = ?11? = no asp mode selected, persiste nt protection mode is the default. ? aspr[2:1] = ?10? = persistent prot ection mode perm anently selected. ? aspr[2:1] = ?01? = password protection mode permanently selected. ? aspr[2:1] = ?00? is an illegal condition, attempting to program more than one bit to zero results in a programming failure. asp register programming rules: ? if the password mode is chosen, the pa ssword must be programmed prior to se tting the protection mode lock bits. ? once the protection mode is selected, the following otp conf iguration register bits are permanently protected from programming and no further changes to the otp register bits is allowed: ? cr1nv[5:2] ?cr2nv ?cr3nv ?cr4nv ? aspr ? pass ?nvdlr ? if an attempt to change any of the registers above, a fter the asp mode is selected, the operation will fail and p_err (sr1v[6]) will be set to 1. the programming time of the asp register is the same as the ty pical page programming time. the system can determ ine the status of the asp register programming operation by re ading the wip bit in the status register. see status register 1 on page 51 for information on wip. see sector protection states summary on page 73 . 8.4.2 persistent protection bits the persistent protecti on bits (ppb) are located in a separate non-volatile flash array. one of the ppb bits is related to each sector. when a ppb is 0, its related se ctor is protected from program and erase operat ions. the ppb are programm ed individually but mus t be erased as a group, similar to the way individual words may be pr ogrammed in the main array but an entire sector must be eras ed at the same time. the ppb have the same program and erase e ndurance as the main flash memory array. preprogramming and verification prior to erasure are handled by the device. programming a ppb bit requires t he typical page programming time. erasing all the ppbs requires typical se ctor erase time. duri ng ppb bit programming and ppb bit erasing, status is available by reading th e status register. reading of a ppb bit requires the initial access time of the device. notes:
document number: 002-00368 rev. *j page 73 of 151 S25FS128S s25fs256s 1. each ppb is individually programmed to 0 and all are erased to 1 in parallel. 2. if the ppb lock bit is 0, the ppb program or ppb erase co mmand does not exec ute and fails without programming or erasing the ppb. 3. the state of the ppb for a given sector c an be verified by using the ppb read command. 8.4.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dyb only control the protecti on for sectors that have their ppb set to 1. by issuing the dyb write command, a dyb is cleared to 0 or set to 1, thus placing each se ctor in the protected or unprotected state res pectively. this feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. the dybs can be set or cleared as often as needed as they are volatile bits. 8.4.4 ppb lock bit (ppbl[0]) the ppb lock bit is a volatile bit for protec ting all ppb bits. when cleared to 0, it locks all ppbs, when set to 1, it allows the ppbs to be changed. see section 7.6.10, ppb lock register (ppbl) on page 65 for more information. the plbwr command is used to clear the ppb lock bit to 0. the ppb lock bit must be clear ed to 0 only after all the ppbs are configured to the desired settings. in persistent protection mode, the ppb lock is set to 1 during por or a ha rdware reset. when cleared to 0, no software command sequence can set the ppb lock bit to 1, only another hardware reset or power-up can set the ppb lock bit. in the password protection mode, the ppb lock bit is cleare d to 0 during por or a hardware reset. the ppb lock bit can only be set to 1 by the password unlock command. 8.4.5 sector protection states summary each sector can be in one of the following protection states: ? unlocked ? the sector is unprotected and protection can be c hanged by a simple command. the protection state defaults to unprotected when the devic e is shipped from cypress. ? dynamically locked ? a sector is protected and protection ca n be changed by a simple command. the protection state is not saved across a power cycle or reset. ? persistently locked ? a sector is protected and protection can only be changed if the ppb lock bit is set to 1. the protection state is non-volatile an d saved across a power cycle or rese t. changing the protection state re quires programming and or erase of the ppb bits. sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected ? ppb and dyb are changeable. 1 1 0 protected ? ppb and dyb are changeable. 1 0 1 protected ? ppb and dyb are changeable. 1 0 0 protected ? ppb and dyb are changeable. 0 1 1 unprotected ? ppb not changeable, dyb is changeable. 0 1 0 protected ? ppb not changeable, dyb is changeable. 0 0 1 protected ? ppb not changeable, dyb is changeable. 0 0 0 protected ? ppb not changeable, dyb is changeable.
document number: 002-00368 rev. *j page 74 of 151 S25FS128S s25fs256s 8.4.6 persistent protection mode the persistent protec tion method sets the ppb lock bit to 1 during por or hardware reset so t hat the ppb bits are unprotected b y a device hardware reset. softwa re reset does not affect the ppb lock bit. the plbwr command can clear the ppb lock bit to 0 to protect the ppb. there is no command to set the ppb lock bit therefore the ppb lock bit will remain at 0 until the next power-o ff or hardware reset. 8.4.7 password protection mode password protection mode allows an even higher level of security t han the persistent sector protec tion mode, by requiring a 64- bit password for unlocking the ppb lock bit. in addition to this password requirement, after powe r-up and hardware reset, the ppb lock bit is cleared to 0 to ensure protection at power-up. su ccessful execution of the passwor d unlock command by entering the entire password sets the ppb lock bit to 1, allowing for sector ppb modifications. password protection notes: ? once the password is programmed and verified, the password mode (aspr[2]=0) must be set in order to prevent reading the password. ? the password program command is only capable of programming 0s . programming a 1 after a cell is programmed as a 0 results in the cell left as a 0 with no programming error set. ? the password is all 1s when shipped from cy press. it is located in its own memory space and is accessible through the use of th e password program, password read, rdar, and wrar commands. ? all 64-bit password combinations are valid as a password. ? the password mode, once programmed, prevents reading the 64 -bit password and further passw ord programming. all further program and read commands to the password region are disabled an d these commands are ignored or return undefined data. there is no means to verify what the password is after the password mode lock bit is sele cted. password verification is only allowed before selecting the password protection mode. ? the protection mode lock bits are not erasable. ? the exact password must be entered in order for the unlocking function to occur. if the password unlock command provided password does not match the hidden internal password, the unlock operation fails in the same ma nner as a programming operation on a protected sector. the p_err bit is set to 1, the wip bit remains set, and the ppb lock bit remains cleared to 0. ? the password unlock command cannot be accepted any faster th an once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run thro ugh all the 64-bit combinations in an attempt to correctly ma tch a password. the read status register 1 command may be used to r ead the wip bit to determine when the device has completed the password unlock command or is ready to accept a new passwor d command. when a valid password is provided the password unlock command does not insert the 100 s delay before returning the wip bit to 0. ? if the password is lost after se lecting the password mode, there is no way to set the ppb lock bit. ? ecc status may only be read from sectors that are readable. in read protection mode the addresse s are forced to the boot sector address. ecc status is only in that se ctor while read protection mode is active. 8.5 recommended protection process during system manufacture, the flash dev ice configuration should be defined by: 1. programming the otp configuration bits in cr1n v[5, 3:2], cr2nv, cr3nv, and cr4nv as desired. 2. program the secure silicon region (otp area) as desired. 3. program the ppb bits as de sired via the ppbp command. 4. program the non-volatile data learning pattern (n vdlr) if it will be used in ddr read commands. 5. program the password register (pass) if password protection will be used. 6. program the asp register as desired, including the selectio n of the persistent or passw ord asp protection mode in aspr[2:1]. it is very important to explicitly select a protec tion mode so that later accidental or malicious programming of the asp register and otp configuration is prevented. this is to ensure that only the intended otp protection and configuration features are enabled.
document number: 002-00368 rev. *j page 75 of 151 S25FS128S s25fs256s during system power-up and boot code execution: 1. trusted boot code can determine whether there is any need to program additional ssr (otp area) information. if no ssr changes are needed the freeze bit (cr1v[0]) can be set to 1 to protect the ssr from cha nges during the remainder of normal system operation while power remains on. 2. if the persistent protection mode is in use, trusted boot code can determine w hether there is any need to modify the persistent (ppb) sector protection via the ppbp or ppbe commands. if no ppb changes are needed the ppblock bit can be cleared to 0 via the ppbl to protect the ppb bits fr om changes during the remainde r of normal syst em operation while power remains on. 3. the dynamic (dyb) sector protection bits can be written as desired via the dybar.
document number: 002-00368 rev. *j page 76 of 151 S25FS128S s25fs256s 9. commands all communication between the host system and s25fs-s family memory devices is in the form of units called commands. all commands begin with an instruction that selects the type of information transfer or device operation to be performed. comma nds may also have an address, instruction modifier, latency period, da ta transfer to the memory, or data transfer from the memory. all instruction, address, and data information is transfe rred sequentially between the host system and memory device. command protocols are also classified by a numerical nomenclatur e using three numbers to referenc e the transfer width of three command phases: ? instruction; ? address and instruction modifier (mode); ? data. single bit wide commands start with an instruction and may provide an address or data, all sent only on the si signal. data may be sent back to the host serially on the so signal. this is refere nced as a 1-1-1 command protocol for single bit width instructio n, single bit width address and modifier, single bit data. dual or quad input / output (i/o ) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibb le) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) grou ps on io0, io1, io2, and io3. this is referenced as 1-2-2 fo r dual i/o and 1-4-4 for quad i/o command protocols. the s25fs-s family also supports a qpi mode in which all informa tion is transferred in 4-bit width, including the instruction, address, modifier, and data. this is refer enced as a 4-4-4 command protocol. commands are structured as follows: ? each command begins with an eight bit (b yte) instruction. however, some read commands are modified by a prior read command, such that the instruction is imp lied from the earlier command. this is ca lled continuous read mode. when the device is in continuous read mode, the instruction bits are not transmitted at the beginning of the comma nd because the instruction is th e same as the read command that initiated the continuous read mode. in continuous read mode the command will begin with the read address. thus, continuous read mode removes eight instructi on bits from each read command in a series of same type read commands. ? the instruction may be stand alone or may be followed by address bi ts to select a location within one of several address spaces in the device. the address may be either a 24-bit or 32-bit, byte boundary, address. ? the serial peripheral interface with multiple io provides the op tion for each transfer of address and data information to be do ne one, two, or four bits in parallel. this enables a trade off between the number of signal connections (io bus width) and the sp eed of information transfer. if the host system ca n support a two or four bit wide io bus the memory performance can be increased by u sing the instructions that provide parallel 2-bi t (dual) or parallel 4-bit (quad) transfers. ? in legacy spi multiple io mode, the width of all transfers following the instruction are determined by the instruction sent. fo llowing transfers may continue to be single bit serial on only the si or serial output (so) signals, they may be done in two bit groups per (dual) transfer on the io0 and io1 signals, or they may be done in 4-bit groups per (quad) transfer on the io0-io3 signals. wit hin the dual or quad groups the least significant bit is on io0. more si gnificant bits are placed in si gnificance order on each higher numbered io signal. single bits or parallel bit groups are tr ansferred in most to least significant bit order. ? in qpi mode, the width of all transfers, including instruct ions, is a 4-bit wide (quad) transfer on the io0-io3 signals. ? dual i/o and quad i/o read instructions send an instruction modi fier called mode bits, following the address, to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. the next command thus does not pro vide an instruction byte, only a new address and mode bits. this r educes the time needed to send each command when the same command type is repeated in a sequence of commands. ? the address or mode bits may be followed by write data to be st ored in the memory device or by a read latency period before read data is returned to the host. ? read latency may be zero to several sck cycl es (also referred to as dummy cycles). ? all instruction, address, mode, and data information is transferr ed in byte granularity. addresses are shifted into the device with the most significant byte first. all data is transferred with th e lowest address byte sent first. following bytes of data are s ent in lowest to highest byte address order i.e. the byte address increments.
document number: 002-00368 rev. *j page 77 of 151 S25FS128S s25fs256s ? all attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will continue to execute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descripti ons. while a program, erase, or write operation is in progres s, it is recommended to check that the write-in progress (wip) bit is 0 before issuing most commands to the device, to ensure the new command can be accepted. ? depending on the command, the time for execution varies. a co mmand to read status information from an executing command is available to determine when the command complete s execution and whether the command was successful. ? although host software in some cases is used to directly cont rol the spi interface signals, the hardware interfaces of the host system and the memory device generally handle the details of si gnal relationships and timing. for this reason, signal relations hips and timing are not covered in detail within this software interfac e focused section of the document. instead, the focus is on t he logical sequence of bits transferred in each command rather than the signal timing and relationships. following are some general signal relationship descriptions to keep in mind. for additional informa tion on the bit level format an d signal timing relationships o f commands, see command protocol on page 14 . ? the host always controls the chip select (cs#), serial clock (sck), and serial input (si) - si for single bit wide transfers. the memory drives serial output (so) for si ngle bit read transfers. the host and memory alternately drive the io0-io3 signals during dual and quad transfers. ? all commands begin with the host selecting the memory by driving cs# low before th e first rising edge of sck. cs# is kept low throughout a command and when cs# is returned high the command ends. generally, cs# remains low for eight bit transfer multiples to transfer byte granular ity information. some commands will not be accepted if cs# is returned high not at an 8-bit boundary.
document number: 002-00368 rev. *j page 78 of 151 S25FS128S s25fs256s 9.1 command set summary 9.1.1 extended addressing to accommodate addressing abov e 128 mb, there are two options: 1. instructions that always require a 4-byte addr ess, used to access up to 32 gb of memory: 2. a 4-byte address mode for backward compatibility to the 3- byte address instructions. the standard 3-byte instructions can be used in conjunction with a 4-byte address mode cont rolled by the address length conf iguration bit (c r2v[7]). the default value of cr2v[7] is loaded from cr2nv[7] (following power-up, hardware reset, or software reset), to enable default 3-byte (24-bit) or 4-byte (32-bit) addressing. when the address length (cr2v[7]) set to 1, the legacy commands are changed to require 4-bytes (32-bits) for the address field. the following instructions can be used in conjunction with the 4-byte address mode configuration to switch from 3 bytes to 4 bytes of address field. command name function instruction (hex) 4read read 13 4fast_read read fast 0c 4dior dual i/o read bc 4qior quad i/o read ec 4ddrqior ddr quad i/o read ee 4pp page program 12 4p4e parameter 4-kb erase 21 4se erase 64/256 kb dc 4eccrd ecc status read 18 4dybrd dyb read e0 4dybwr dybwr e1 4ppbrd ppb read e2 4ppbp ppb program e3 command name function instruction (hex) read read 03 fast_read read fast 0b dior dual i/o read bb qior quad i/o read eb ddrqior ddr quad i/o read) ed pp page program 02 p4e parameter 4-kb erase 20 se erase 64 / 256 kb d8 rdar read any register 65 wrar write any register 71 ees evaluate erase status d0 otpp otp program 42 otpr otp read 4b eccrd ecc status read 19 dybrd dyb read fa dybwr dybwr fb ppbrd ppb read fc ppbp ppb program fd
document number: 002-00368 rev. *j page 79 of 151 S25FS128S s25fs256s 9.1.2 command summary by function s25fs-s family command set (sor ted by function) (sheet 1 of 2) function command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi read device id rdid read id (jedec manufacturer id and jedec cfi) 9f 133 0 yes rsfdp read jedec serial flash discoverable parameters 5a 50 3 yes rdqid read quad id af 133 0 yes register access rdsr1 read status register 1 05 133 0 yes rdsr2 read status register 2 07 133 0 no rdcr read configuration register 1 35 133 0 no rdar read any register 65 133 3 or 4 yes wrr write register (status 1, configuration 1) 01 133 0 yes wrdi write disable 04 133 0 yes wren write enable 06 133 0 yes wrar write any register 71 133 3 or 4 yes clsr clear status register 1 - erase/prog. fail reset this command may be disabled and the instruction value instead used for a program / erase resume command - see configuration register 3 on page 60 30 133 0 yes clsr clear status register 1 (alternate instruction) - erase/prog. fail reset 82 133 0 yes 4bam enter 4-byte address mode b7 133 0 no sbl set burst length c0 133 0 no ees evaluate erase status d0 133 3 or 4 yes eccrd ecc read 19 133 3 or 4 yes 4eccrd ecc read 18 133 4 yes dlprd data learning pattern read 41 133 0 no pnvdlr program nv data learning register 43 133 0 no wvdlr write volatile data learning register 4a 133 0 no read flash array read read 03 50 3 or 4 no 4read read 13 50 4 no fast_read fast read 0b 133 3 or 4 no 4fast_read fast read 0c 133 4 no dior dual i/o read bb 66 3 or 4 no 4dior dual i/o read bc 66 4 no qior quad i/o read eb 133 3 or 4 yes 4qior quad i/o read ec 133 4 yes ddrqior ddr quad i/o read ed 80 3 or 4 yes 4ddrqior ddr quad i/o read ee 80 4 yes program flash array pp page program 02 133 3 or 4 yes 4pp page program 12 133 4 yes erase flash array p4e parameter 4-kb sector erase 20 133 3 or 4 yes 4p4e parameter 4-kb sector erase 21 133 4 yes se erase 64 kb or 256 kb d8 133 3 or 4 yes 4se erase 64 kb or 256 kb dc 133 4 yes be bulk erase 60 133 0 yes be bulk erase (alternate instruction) c7 133 0 yes
document number: 002-00368 rev. *j page 80 of 151 S25FS128S s25fs256s note: 1. commands not supported in qpi mode have undefined behavior if sent when the device is in qpi mode. 9.1.3 read device identification there are multiple commands to read information about the device manufacturer, device type, and device features. spi memories from different vendors have used different commands and formats for reading information about the memories. the s25fs-s family supports the three device information commands. 9.1.4 register read or write there are multiple registers for reporting embedded operation st atus or controlling device c onfiguration options. there are commands for reading or writing these registers. registers contai n both volatile and non-volatile bits. non-volatile bits in re gisters are automatically erased and programmed as a single (write) operation. erase /program suspend /resume eps erase / program suspend 75 133 0 yes eps erase / program suspend (alternate instruction) 85 133 0 yes eps erase / program suspend (alternate instruction) b0 133 0 yes epr erase / program resume 7a 133 0 yes epr erase / program resume (alternate instruction) 8a 133 0 yes epr erase / program resume (alternate instruction) this command may be disabled and the instruction value instead used for a clear status command - see configuration register 3 on page 60 30 133 0 yes one-time program array otpp otp program 42 133 3 or 4 no otpr otp read 4b 133 3 or 4 no advanced sector protection dybrd dyb read fa 133 3 or 4 yes 4dybrd dyb read e0 133 4 yes dybwr dyb write fb 133 3 or 4 yes 4dybwr dyb write e1 133 4 yes ppbrd ppb read fc 133 3 or 4 no 4ppbrd ppb read e2 133 4 no ppbp ppb program fd 133 3 or 4 no 4ppbp ppb program e3 133 4 no ppbe ppb erase e4 133 0 no asprd asp read 2b 133 0 no aspp asp program 2f 133 0 no plbrd ppb lock bit read a7 133 0 no plbwr ppb lock bit write a6 133 0 no passrd password read e7 133 0 no passp password program e8 133 0 no passu password unlock e9 133 0 no reset rsten software reset enable 66 133 0 yes rst software reset 99 133 0 yes reset legacy software reset f0 133 0 no mbr mode bit reset ff 133 0 yes dpd dpd enter deep power-down mode b9 133 0 yes res release from deep power-down mode ab 133 0 yes s25fs-s family command set (sor ted by function) (sheet 2 of 2) function command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi
document number: 002-00368 rev. *j page 81 of 151 S25FS128S s25fs256s 9.1.4.1 monitoring operation status the host system can determine when a write, pr ogram, erase, suspend or ot her embedded o peration is complete by monitoring the write-in-progress (wip) bit in the status register. the read from status register 1 command or read any register command provides the state of the wip bit. the progr am error (p_err) and erase error (e_err) bits in the status register indicate wheth er the most recent program or erase command has not completed succe ssfully. when p_err or e_err bits are set to 1, the wip bit will remain set to one indicating the device remains busy and u nable to receive most new operation commands. only status read (rdsr1 05h), read any register (rdar 65h), status clear (c lsr 30h or 82h), and software reset (rsten 66h, rst 99h or reset f0h) are valid commands when p_err or e_err is set to 1. a clear status regi ster (clsr) followed by a write disable (wrdi) command must be sent to return t he device to standby state. clear status re gister clears the wip, p_err, and e_err bits. wrdi clears the wel bit. alternativel y, hardware reset, or softwa re reset (rst or reset) may be used to return the device to standby state. 9.1.4.2 configuration there are commands to read, write, and prot ect registers that control interface path width, interface timing, interface address length, and some aspects of data protection. 9.1.5 read flash array data may be read from the memory starting at any byte boundary. data bytes are sequ entially read from incrementally higher byte addresses until the host ends the data transfer by driving cs# i nput high. if the byte address reaches the maximum address of t he memory array, the read will continue at address zero of the array. there are several different read commands to specify different access latency and data path widths. double data rate (ddr) commands also define the address and data bit relationship to both sck edges: ? the read command provides a single address bit per sck rising edge on the si signal with read data returning a single bit per sck falling edge on the so signal. this command has zero latency between the address and the returning data but is limited to a maximum sck rate of 50mhz. ? other read commands have a latency period between the address a nd returning data but can operat e at higher sck frequencies. the latency depends on a configuration register read latency value. ? the fast read command provides a single address bit per sck risi ng edge on the si signal with read data returning a single bit per sck falling edge on the so signal. ? dual or quad i/o read commands provide address two bits or four bits per sck rising edge with read data returning two bits, or four bits of data per sck fa lling edge on the io0-io3 signals. ? quad double data rate read commands provide address four bits per every sck edge with read data returning four bits of data per every sck edge on the io0-io3 signals. 9.1.6 program flash array programming data requires two commands: write enable (wren) , and page program (pp). the page program command accepts from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed in one operation. programming means that bits ca n either be left at 1, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. 9.1.7 erase flash array the parameter sector erase, sector erase, or bulk erase commands set all the bits in a sector or the entire memory array to 1. a bit needs to be first erased to 1 before programming can change it to a 0. while bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide or arra y-wide (bulk) level. the write en able (wren) command must precede an erase command. 9.1.8 otp, block protection, an d advanced sector protection there are commands to read and program a separate one-time programmable (otp) array for permanent data such as a serial number. there are commands to control a contiguous group (block) of flash memory array sectors th at are protected from program and erase operations. there are commands to control which individual flash memory a rray sectors are protected from program and erase operations.
document number: 002-00368 rev. *j page 82 of 151 S25FS128S s25fs256s 9.1.9 reset there are commands to reset to the default conditions present af ter power-on to the device. however, the software reset command s do not affect the curre nt state of the freeze or ppb lock bi ts. in all other respects a software reset is the same as a hardwar e reset. there is a command to reset (exit from) the continuous read mode. 9.1.10 dpd a deep power-down (dpd) mode is supported by the fs-s family of devices. if the device has been placed in dpd mode by the dpd (b9h) command, the interface standby current is i dpd . the dpd command is accepted only while the device is not performing an embedded operation as indicated by the status register-1 volatile write in pr ogress (wip) bit being cleared to zero (sr1v[0] = 0). while in dpd mode, the device ignores all comm ands except the release from dp d (res abh) command, that will return the device to the interface standby state after a delay of t res . 9.1.11 reserved some instructions are reserved for future use. in this generati on of the s25fs-s family some of these command instructions may be unused and not affect dev ice operation, some may have undefined results. some commands are reserved to ensure that a legacy or alternate source device command is allowed without effect. this allows legacy software to issue some commands that are not relevant for the current generation s25fs-s family with the assurance these commands do not cause some unexpected action. some commands are reserved for use in special versions of the fs -s not addressed by this document or for a future generation. this allows new host memory controller designs to plan the fl exibility to issue these command instructions. the command format is defined if known at the time this document revision is published. 9.2 identification commands 9.2.1 read identifi cation (rdid 9fh) the read identification (rdid) co mmand provides read access to manufacturer iden tification, device ident ification, and common flash interface (cfi) information. the manufacturer identification is assigned by jedec. the cfi structure is defined by jedec standard. the device identification and cfi values are assigned by cypress. the jedec common flash interface (cfi) specification defines a de vice information structure, which allows a vendor-specified software flash management program (driver) to be used for entire fa milies of flash devices. software support can then be device - independent, jedec manufacturer id independent , forward and backward-compatible for the specified flash device families. system vendors can standardize t heir flash drivers for long-term software compatib ility by using the cfi values to configure a family driver from the cfi information of the device in use. any rdid command issued while a program, erase, or write cycle is in progress is ignored and has no effect on execution of the program, erase, or write cycle that is in progress. the rdid instruction is shifted on si. after the last bit of the rdid instruction is sh ifted into the device, a byte of manufac turer identification, two bytes of dev ice identification, extended device identification, and cfi information will be shifted sequent ially out on so. as a whole this information is referred to as id-cfi. see device id and common flash interface (id-cfi) address map on page 126 for the detail description of the id-cfi contents. continued shifting of output bey ond the end of the defined id-cfi address spac e will provide undefined data. the rdid command sequence is terminated by driving cs# to the logic high state anytime during data output. the maximum clock frequency for the rdid command is 133 mhz.
document number: 002-00368 rev. *j page 83 of 151 S25FS128S s25fs256s figure 9.1 read identification (rdid) command sequence this command is also supported in qpi mode. in qpi mode the inst ruction is shifted in on io0-io3 and the returning data is shif ted out on io0-io3. figure 9.2 read identification (rdi d) qpi mode command 9.2.2 read quad identification (rdqid afh) the read quad identification (rdqid) comman d provides read access to manufacturer id entification, device identification, and common flash interface (cfi) information. this command is an alternate way of reading the same information provided by the rdid command while in qpi mode. in all other respects the command behaves the same as the rdid command. the command is recognized only when the device is in qpi mode (cr2v[6]=1). the instruction is shifted in on io0-io3. after the last bit of the instruction is shifted into the device, a byte of manufactur er identification, two bytes of device identification, e xtended device identification, and cfi information will be shifted sequenti ally out on io0-io3. as a whol e this information is referred to as id- cfi. see device id and common flash interface (id-cfi) address map on page 126 for the detail descri ption of the id-cfi contents. continued shifting of output bey ond the end of the defined id-cfi address space will provide undefined data. the command sequence is terminated by driving cs# to the logic high state anytime during data output. the maximum clock frequency for the command is 133 mhz. figure 9.3 read quad identification (rdqid) command sequence 9.2.3 read serial flash discover able parameters (rsfdp 5ah) the command is initiated by shifting on si the instruction code ?5ah?, followed by a 24-bit address of 000000h, followed by 8 d ummy cycles. the sfdp bytes are then shifted out on so starting at the fallin g edge of sck after the dummy cycles. the sfdp bytes ar e always shifted out with the msb first. if the 24 -bit address is set to any other value, the selected location in the sfdp space is the cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n cs# sck io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 instruction d1 d2 d3 d4 d5 cs# sck io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 instruction d1 d2 d3 d4 d5
document number: 002-00368 rev. *j page 84 of 151 S25FS128S s25fs256s starting point of the data read. this enables random access to any parameter in the sfdp space. the rsfdp command is supported up to 50 mhz. figure 9.4 rsfdp command sequence this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0? io3 and the returning data is shif ted out on io0?io3. figure 9.5 rsfdp qpi mode command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sck io0 io1 io2 io3 phase 4 0 20 4 0 4 0 4 0 4 0 4 0 5 1 21 5 1 5 1 5 1 5 1 5 1 6 2 22 6 2 6 2 6 2 6 2 6 2 7 3 23 7 3 7 3 7 3 7 3 7 3 instruct. address dummy d1 d2 d3 d4
document number: 002-00368 rev. *j page 85 of 151 S25FS128S s25fs256s 9.3 register access commands 9.3.1 read status regi ster 1 (rdsr1 05h) the read status register 1 (rdsr1) command allows the status register 1 contents to be read from so . the volatile version of status register 1 (sr1v) contents may be read at any time, even while a progra m, erase, or write operat ion is in progress. it i s possible to read status register 1 contin uously by providing multiples of eight clo ck cycles. the status is updated for each ei ght cycle read. the maximum clock frequency for the rdsr1 (05h) command is 133 mhz. figure 9.6 read status register 1 (rdsr1) command sequence this command is also supported in qpi mode. in qpi mode the inst ruction is shifted in on io0-io3 and the returning data is shif ted out on io0-io3, two clock cycles per byte. figure 9.7 read status register 1 (rdsr1) qpi mode command 9.3.2 read status regi ster 2 (rdsr2 07h) the read status register 2 (rdsr2) comman d allows the status register 2 contents to be read from so. the status register 2 contents may be read at any time, even while a program, erase, or write operation is in progress. it is possible to read the st atus register 2 continuously by prov iding multiples of eight clock cycles. the status is updated fo r each eight cycl e read. the maxi mum clock frequency for the rds r2 command is 133 mhz. figure 9.8 read status register 2 (rdsr2) command in qpi mode, status register 2 may be r ead via the read any register command, see read any register (rdar 65h) on page 92 cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status cs# sck io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 instruct. d1 d2 d3 d4 d5 cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status
document number: 002-00368 rev. *j page 86 of 151 S25FS128S s25fs256s 9.3.3 read configurati on register (rdcr 35h) the read configuration register (rdcr) command allows the volatile configuration register (cr1v) contents to be read from so. it is possible to read cr1v continuously by providing multiples of eight clock cycles. the configuration register contents may be read at any time, even while a program, er ase, or write operation is in progress. figure 9.9 read configuration register (rdcr) command sequence in qpi mode, configuration register 1 may be read via the read any register command, see section 9.3.13, read any register (rdar 65h) on page 92 9.3.4 write registers (wrr 01h) the write registers (wrr) command allows new values to be writ ten to both the status register 1 and configuration register 1. before the write registers (wrr) command can be accepted by the device, a write enable (wren) command must be received. after the write enable (wren) command has been decoded successfu lly, the device will set the write enable latch (wel) in the status register to enab le any write operations. the write registers (wrr) command is entered by shifting the instruction and the data bytes on si. the stat us register is one d ata byte in length. the wrr operation first erases the regi ster then programs the new value as a si ngle operation. the write registers (wrr) command will set the p_err or e_err bits if th ere is a failure in the wrr operation. see status register 1 volatile (sr1v) on page 52 for a description of the error bits. any st atus or configuration register bit reserv ed for the future must be written as a 0. cs# must be driven to the logic high state after the eighth or sixteenth bit of data has been la tched. if not, the write regist ers (wrr) command is not executed. if cs# is driven high after the eigh th cycle then only the status regi ster 1 is written; otherwise, aft er the sixteenth cycle both the status and co nfiguration registers are written. as soon as cs# is driven to the logic hi gh state, the self-tim ed write registers (wrr) operation is initiated. while the write registers (wrr) operation is in progress, t he status register may still be read to c heck the value of the write-in progress (wi p) bit. the write-in progress (wip) bit is a 1 during the self-timed writ e registers (wrr) operation, and is a 0 when it is completed. when the write registers (wrr) operation is comple ted, the write enable latch (wel) is set to a 0. the maximum clock frequency for t he wrr command is 133 mhz. this command is also supported in qpi mode. in qpi mode the inst ruction and data is shifted in on io0?io3, two clock cycles per byte. figure 9.10 write registers (wrr) command sequence ? 8-data bits cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register 1
document number: 002-00368 rev. *j page 87 of 151 S25FS128S s25fs256s figure 9.11 write registers (wrr) command sequence ? 16-data bits figure 9.12 write registers (wrr) command sequence ? 16-data bits qpi mode the write registers (wrr) command allows th e user to change the values of the block protect (bp2, bp1, and bp0) bits in either the non-volatile status register 1 or in the volatile status register 1, to define the si ze of the area that is to be treated as read-only. the bpnv_o bit (cr1nv[3]) controls whethe r wrr writes the non-volatile or volati le version of status register 1. when cr1nv[3] = 0 wrr writes sr1nv[4:2]. when cr1nv[3] = 1 wrr writes sr1v[4:2]. the write registers (wrr) command also allows the user to set the status register writ e disable (srwd) bit to a 1 or a 0. the status register write disable (srwd) bit and write protect (wp#) signal allow the bp bits to be hardware protected. when the status register write disable (srw d) bit of the status register is a 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previous ly been set by a write enable (wren) command, regardless of the whether write protect (wp#) signal is driven to the logic high or logic low state. when the status register write disable (srw d) bit of the status register is set to a 1, two cases need to be considered, depend ing on the state of write protect (wp#): ? if write protect (wp#) signal is driven to the logic high state, it is possible to write to the status and configuration regist ers provided that the write enable latch (wel) bit has previously been set to a 1 by initiating a write enable (wren) command. ? if write protect (wp#) signal is driven to the logic low state, it is not possible to write to the status and configuration reg isters even if the write enable latch (wel) bit has previously been set to a 1 by a write enable (wren) command. attempts to write to the status and configuration registers ar e rejected, not accepted for execution, and no error indication is provided. as a consequence, all the data bytes in the memory area that are protected by the block pr otect (bp2, bp1, bp0) bits of the status register, are also hardware protected by wp#. the wp# hardware protection can be provided: ? by setting the status register write disable (srwd) bit afte r driving write protect (wp#) signal to the logic low state; ? or by driving write protect (wp#) signal to the logic low state af ter setting the status register write disable (srwd) bit to a 1. the only way to release the hardware protec tion is to pull the write protect (wp#) sig nal to the logic high state. if wp# is permanently tied high, hardware protection of the bp bits can never be activated. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register 1 input configuration register 1 cs# sck io0 io1 io2 io3 phase 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 instruct. input status input config
document number: 002-00368 rev. *j page 88 of 151 S25FS128S s25fs256s notes: 1. the status register originally shows 00h when the de vice is first shipped from cypress to the customer. 2. hardware protection is disabled when quad mode is enabled (cr1v[ 1] = 1). wp# becomes io2; therefore, it cannot be utilized. 9.3.5 write enable (wren 06h) the write enable (wren) command sets the write enable latch (w el) bit of the status register 1 (sr1v[1]) to a 0. the write enable latch (wel) bit must be set to a 1 by issuing the wr ite enable (wren) command to enable write, program and erase commands. cs# must be driven into the logic high st ate after the eighth bit of the instruction byte has been latched in on si. without cs # being driven to the logic high state after the eighth bit of the instru ction byte has been latched in on si, the writ e enable operati on will not be executed. figure 9.13 write enable (wren) command sequence this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0-io3, two clock cycles per byte. figure 9.14 write enable (wren) command sequence qpi mode 9.3.6 write disable (wrdi 04h) the write disable (wrdi) command clears the write enable la tch (wel) bit of the status register 1 (sr1v[1]) to a 1. the write enable latch (wel) bit may be cleared to a 0 by i ssuing the write disable (wrdi) co mmand to disable page program (pp), sector erase (se), bulk erase (be), write registers (w rr or wrar), otp program (otpp), and other commands, that require wel be set to 1 for execution. the wrdi command can be used by the user to protect me mory areas against inadvertent block protection modes wp# srwd bit mode write protection of registers memory content protected area unprotected area 11 software protected status and configuration registers are writable (if wren command has set the wel bit). the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register can be changed. protected against page program, sector erase, and bulk erase. ready to accept page program, and sector erase commands. 10 00 01 hardware protected status and configuration registers are hardware write protected. the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register cannot be changed. protected against page program, sector erase, and bulk erase. ready to accept page program or erase commands. cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
document number: 002-00368 rev. *j page 89 of 151 S25FS128S s25fs256s writes that can possibly corrupt the contents of the memory. the wrdi command is ignored during an embedded operation while wip bit =1. cs# must be driven into the logic high st ate after the eighth bit of the instruction byte has been latched in on si. without cs # being driven to the logic high state after the eighth bit of the instru ction byte has been latched in on si, the write disable operat ion will not be executed. figure 9.15 write disable (wrdi) command sequence this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. figure 9.16 write disable (wrdi) command sequence qpi mode 9.3.7 clear status regi ster (clsr 30h or 82h) the clear status register command resets bit sr1v[5] (erase fa il flag) and bit sr1v[6] (program fail flag). it is not necessary to set the wel bit before a clear status regist er command is executed. the clear status register command will be accepted even when the device remains busy with wip set to 1, as the device does remain busy when either error bit is set. the wel bit will b e unchanged after this command is executed. the legacy clear status register (clsr 30h) instruction may be disabled and the 30h instruction value instead used for a progra m / erase resume command - see configuration register 3 on page 60 . the clear status register alte rnate instruction (clsr 82h) is always available to clear the status register. figure 9.17 clear status register (clsr) command sequence this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00368 rev. *j page 90 of 151 S25FS128S s25fs256s figure 9.18 clear status register (clsr) command sequence qpi mode 9.3.8 ecc status register read (eccrd 19h or 4eecrd 18h) to read the ecc status register, the command is followed by the ecc unit address, the four least significant bits (lsb) of addr ess must be set to zero. this is followed by the number of dummy cycles selected by the read laten cy value in cr2v[3:0]. then the 8 -bit contents of the ecc register, for the ecc unit selected, are shif ted out on so 16 times, once for each byte in the ecc unit. if cs# remains low the next ecc unit status is sent through so 16 times, once for each byte in the ecc unit. the maximum operating clock frequency for the ecc read command is 133 mhz. figure 9.19 ecc status register read command sequence note 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command 19h. 2. a = msb of address = 31 with command 18h this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0-io3, two clock cycles per byte. figure 9.20 eccrd (19h) o r 4eccrd (18h), qpi mode, command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command 19h. 2. a = msb of address = 31 with command 18h. cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 7 3 7 3 instruct. address dummy d1 d2 d3 d4
document number: 002-00368 rev. *j page 91 of 151 S25FS128S s25fs256s 9.3.9 program nvdlr (pnvdlr 43h) before the program nvdlr (pnvdlr) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device will set the write enable latch (wel) to enable the pnvdlr operation. the pnvdlr command is entered by shifting the instruction and the data byte on si. cs# must be driven to the logic high state after the eighth bit of data has been latche d. if not, the pnvdlr command is not executed. as soon as cs# is driven to t he logic high state, the self-timed pnvdlr operation is initiated. while the pnvdlr operation is in progress, the status regi ster may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed pnvdlr cycle, and is a 0. when it is completed. the pnvdlr operation can report a program error in the p_err bit of the status register. when the pnvdlr operation is completed, th e write enable latch (wel) is set to a 0. the maximum clock frequency for the pnvdlr command is 133 mhz. figure 9.21 program nvdlr (pnvdlr) command sequence 9.3.10 write vdlr (wvdlr 4ah) before the write vdlr (wvdlr) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) comman d has been decoded successfully, the device will set the write enable latch (wel) to enable wvdlr operation. the wvdlr command is entered by shifting the instruction and the data byte on si. cs# must be driven to the logic high stat e after the eighth bit of data has been latche d. if not, the wvdl r command is not exec uted. as soon as cs# is driven to the logic high state, the wvdlr operation is initiated with no del ays. the maximum clock frequency for the pnvdlr command is 133 mhz. figure 9.22 write vdlr (wvdlr) command sequence 9.3.11 data learning pa ttern read (dlprd 41h) the instruction is shifted on si , then the 8-bit dlp is shifted out on so. it is possible to read the dlp continuously by provi ding multiples of eight clock cycles. the maximum operati ng clock frequency for the dlprd command is 133 mhz. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data
document number: 002-00368 rev. *j page 92 of 151 S25FS128S s25fs256s figure 9.23 dlp read (dlprd) command sequence 9.3.12 enter 4-byte a ddress mode (4bam b7h) the enter 4-byte address mode (4bam) command sets the volatile address length bit (cr2v[7]) to 1 to change most 3-byte address commands to require 4 bytes of address. the read sfdp (rsfdp) command is the only 3-byte command that is not affected by the address length bit. rsfdp is required by the je dec jesd216 standard to always have only 3 bytes of address. a hardware or software reset is requ ired to exit the 4-byte address mode. figure 9.24 enter 4-byte address mode (4bam b7h) command sequence 9.3.13 read any re gister (rdar 65h) the read any register (rdar) command provides a way to read all device registers - non-volatile and volatile. the instruction i s followed by a 3- or 4-byte address (depending on the address length configuration cr2v[7], followed by a number of latency (dummy) cycles set by cr2v[3:0]. then the se lected register contents ar e returned. if the read access is continued the same addressed register contents are returned unt il the command is terminated - only one register is read by each rdar command. reading undefined locations provides undefined data. the rdar command may be used during embedded operations to read status register 1 (sr1v). the rdar command is not used for reading re gisters that act as a window into a larger array:eccsr, ppbar, and dybar. there are separate commands required to select and read the location in the array accessed. the rdar command will r ead invalid data from th e pass register locations if the asp passw ord protection mode is selected by programming aspr[2] to 0. register address map byte address (hex) register name description 00000000 sr1nv non-volatile status and configuration registers 00000001 n/a 00000002 cr1nv 00000003 cr2nv 00000004 cr3nv 00000005 cr4nv ... n/a 00000010 nvdlr non-volatile data learning register ... n/a cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00368 rev. *j page 93 of 151 S25FS128S s25fs256s figure 9.25 read any register read command sequence note: 1. a = msb of address = 23 for address length cr2v[7] = 0, or 31 for cr2v[7] = 1 this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0-io3, two clock cycles per byte. 00000020 pass[7:0] non-volatile password register 00000021 pass[15:8] 00000022 pass[23:16] 00000023 pass[31:24] 00000024 pass[39:32] 00000025 pass[47:40] 00000026 pass[55:48] 00000027 pass[63:56] ... n/a 00000030 aspr[7:0] non-volatile 00000031 aspr[15:8] ... n/a 00800000 sr1v volatile status and configuration registers 00800001 sr2v 00800002 cr1v 00800003 cr2v 00800004 cr3v 00800005 cr4v ... n/a 00800010 vdlr volatile data learning register ... n/a 00800040 ppbl volatile ppb lock register ... n/a register address map byte address (hex) register name description cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
document number: 002-00368 rev. *j page 94 of 151 S25FS128S s25fs256s figure 9.26 read any register, qpi mode, command sequence note: a = msb of address = 23 for address length cr2v[7] = 0, or 31 for cr2v[7] = 1 9.3.14 write any register (wrar 71h) the write any register (wrar) command prov ides a way to write any device register - non-volatile or volatile. the instruction i s followed by a 3- or 4-byte address (depending on the address l ength configuration cr2v[ 7], followed by one byte of data to writ e in the address selected register. before the wrar command can be accepted by the device, a wr ite enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the wip bit in sr1v may be checked to determine when the operation is completed. the p_e rr and e_err bits in sr1v may be checked to determine if any error occurred during the operation. some registers have a mixture of bit types and individual rules controlling which bits may be modified. some bits are read only , some are otp. read only bits are never modified and the related bits in the wr ar command data byte are ignored without setting a program or erase error indication (p_err or e_err in sr1v). hence, the value of these bits in the wrar data byte do not matter. otp bits may only be programmed to the level opposite of their de fault state. writing of otp bits back to their default state i s ignored and no error is set. non-volatile bits which are changed by the wrar data, require non-volatile register write time (t w) to be updated. the update process involves an erase and a program operation on the non-volat ile register bits. if either th e erase or program portion of the update fails the related error bit and wip in sr1v will be set to 1. volatile bits which are changed by the wrar data, require the volatile register write time (t cs ) to be updated. status register 1 may be repeatedly read (polled) to monitor the write-in-progress (wip) bit (sr1v[0]) and the error bits (sr1v[6,5]) to determine when the register wr ite is completed or failed. if there is a write failure, the cl ear status command is used to clear the error status and enable the device to return to standby state. however, the ppbl register can not be wr itten by the wrar command. only the ppb lock bit wr ite (plbwr) command can write the ppbl register. the command sequence and behavior is the same as the pp or 4pp command with only a single byte of data provided. see section 9.5.2, page program (pp 02h or 4pp 12h) on page 104 . the address map of the registers is the same as shown for section 9.3.13, read any register (rdar 65h) on page 92 . 9.3.15 set burst length (sbl c0h) the set burst length (sbl) command is used to configure the burst wrap fe ature. burst wrap is used in conjunction with quad i/o read and ddr quad i/o read, in legacy spi or qpi mode, to access a fixed length and alignment of data. certain applications can benefit from this feature by improving t he overall system code execution performance. the burst wrap featur e allows application s that use cache, to start filling a cache li ne with instruction or data from a critic al address first, then fill the remainder o f the cache line afterwards within a fixed length (8/16/32/64-byte s) of data, without issuing multiple read commands. cs# sck io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 7 3 7 3 instruct. address dummy d1 d2 d3 d4
document number: 002-00368 rev. *j page 95 of 151 S25FS128S s25fs256s the set burst length (sbl) command writes the cr4v register to enable or disable the wrapped read feature and set the wrap boundary. when enabled the wrapped read feature changes the related read commands from sequentially reading until the command ends, to reading sequentially wrapped within a group of bytes. when cr4v[4] = 1, the wrap mode is not enabled a nd unlimited length sequential read is performed. when cr4v[4] = 0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes is read starting at t he byte address provided by the read command and wrapping around at the group alignment boundary. the group of bytes is of length and alig ned on an 8-, 16-, 32-, or 64-byte boun dary. cr4v[1:0] selects the boundary. see configuration register 4 volatile (cr4v) on page 62 . the starting address of the read command sele cts the group of bytes and the first data returned is the addressed byte. bytes ar e then read sequentially until the end of the group boundary is reached. if the read cont inues the address wraps to the beginning of the group and continues to read sequentially. this wrapped read sequence continues until the command is ended by cs# returning high. the power-on reset, hardware reset, or software reset default burst length can be changed by programming cr4nv with the desired value using the wrar command. figure 9.27 set burst length command sequence 9.4 read memory array commands read commands for the main flash array provide many options for prior generation spi compatib ility or enhanced performance spi: ? some commands transfer address or data on each rising edge of sck. these are called single data rate commands (sdr). ? some sdr commands transfer address one bit per rising edge of sck and return data 1bit of data per rising edge of sck. these are called single width commands. ? some sdr commands transfer both address and data two or four bits per rising edge of sck. these are called dual i/o for two bits, quad i/o, and qpi for four bits. qpi also transfers instruction four bits per rising edge. example burst wrap sequences cr4v[4,1:0] value (hex) wrap boundary (bytes) start address (hex) address sequence (hex) 1x sequential xxxxxx03 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, ... 00 8 xxxxxx00 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02, ... 00 8 xxxxxx07 07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, ... 01 16 xxxxxx02 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 00, 01, 02, 03, ... 01 16 xxxxxx0c 0c, 0d, 0e, 0f, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, ... 02 32 xxxxxx0a 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, ... 02 32 xxxxxx1e 1e, 1f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 00, ... 03 64 xxxxxx03 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2a, 2b, 2c, 2d, 2e, 2f, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3a, 3b, 3c, 3d, 3e, 3f, 00, 01, 02 ... 03 64 xxxxxx2e 2e, 2f, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3a, 3b, 3c, 3d, 3e, 3f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2a, 2b, 2c, 2d, 2e, 2f, ... cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data
document number: 002-00368 rev. *j page 96 of 151 S25FS128S s25fs256s ? some commands transfer address and data on both the rising edge and falling edge of sck. these are called double data rate (ddr) commands. ? there are ddr commands for 4 bits of address or data per sck edge. these are called quad i/ o ddr and qpi ddr for four bit per edge transfer. all of these commands, except qpi read, beg in with an instruction code that is transf erred one bit per sck rising edge. qpi rea d transfers the instruction four bi ts per sck rising edge.the instruction is followe d by either a 3- or 4-byte address transferre d at sdr or ddr. commands transferring address or data 2 or 4 bits per clock edge are called multiple i /o (mio) commands. for s25fs-s family devices at 256-mbits or higher density, the traditiona l spi 3-byte addresses are unable to directly address all location s in the memory array. separate 4-byte address read commands are prov ided for access to the entire address space. these devices may be configured to take a 4-byte address fr om the host system with t he traditional 3-byte address commands. the 4-byte address mode for traditional commands is activated by setting the address length bit in configuration register 2 to 0. in the fs128s, h igher order address bits above a23 in the 4-byte address commands, or commands using 4-byte address mode are not relevant and are ignored because the flash array is only 128 mbits in size. the quad i/o and qpi commands provide a perform ance improvement option controlled by m ode bits that are sent following the address bits. the mode bits indicate whet her the command following the end of the curr ent read will be another read of the same type, without an instruction at t he beginning of the read. these mode bits give the option to eliminate the instruction cycles when doing a series of quad read accesses. some commands require delay cycles following the address or mode bits to allow time to acce ss the memory array - read latency. the delay or read latency cycles are traditionally called dummy cycl es. the dummy cycles are ignored by the memory thus any dat a provided by the host during these cycles is ?don?t care? and the host may also leave the si signal at high impedance during the dummy cycles. when mio commands are used th e host must stop driving the io signals (outputs are high impedance) before the end of last dummy cycle. when ddr commands are used the host must not drive the i/o signals during any dummy cycle. the number of dummy cycles varies with the sck frequency or per formance option selected via th e configuration register 2 (cr2v[3:0]) latency code. dummy cycles are measured from sc k falling edge to next sck falling edge. spi outputs are traditionally driven to a new value on the falling edge of each sck. zero dummy cycles means the returning data is driven by th e memory on the same falling edge of sck that t he host stops driving address or mode bits. the ddr commands may optionally have an 8-edge data learning patter n (dlp) driven by the memory, on all data outputs, in the dummy cycles immediately before the start of data. the dlp can help the ho st memory controller dete rmine the phase shift from sck to data edges so that the memory controller can capture data at the center of the data eye. when using sdr i/o commands at higher sck frequencies (>50 mhz) , an lc that provides one or more dummy cycles should be selected to allow additional time for the host to stop driving bef ore the memory starts driving data, to minimize i/o driver co nflict. when using ddr i/o commands with t he dlp enabled, an lc that prov ides five or more dummy cycles should be selected to allow one cycle of additional time for t he host to stop dr iving before the memory star ts driving the 4-cycle dlp. each read command ends when cs# is returned high at any point during data return. cs# must not be returned high during the mode or dummy cycles before data returns as this may cause mode bi ts to be captured in correctly; making it indeterminate as to whether the device remains in continuous read mode. 9.4.1 read (read 03h or 4read 13h) the instruction ? 03h (cr2v[7] = 0) is followed by a 3-byte address (a23?a0) or ? 03h (cr2v[7] = 1) is followed by a 4-byte address (a31?a0) or ? 13h is followed by a 4-byte address (a31?a0) then the memory contents, at the address given, are shifted out on so. the maximum operating clock frequency for the read command is 50 mhz. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely.
document number: 002-00368 rev. *j page 97 of 151 S25FS128S s25fs256s figure 9.28 read command sequence (3-byte address, 03h or 13h) note: 1. a = msb of address = 23 for cr2v[7] = 0, or 31 for cr2v[7] = 1 or command 13h. 9.4.2 fast read (fast_read 0bh or 4fast_read 0ch) the instruction ? 0bh (cr2v[7] = 0) is followed by a 3-byte address (a23?a0) or ? 0bh (cr2v[7] = 1) is followed by a 4-byte address (a31?a0) or ? 0ch is followed by a 4-byte address (a31?a0) the address is followed by dummy cycles depending on the latency code set in the configuration register cr2v[3:0]. the dummy cycles allow the device internal circuits additional time for accessing the initial address locati on. during the dummy cycles t he data value on so is ?don?t care? and may be high impedance. then t he memory contents, at the address given, are shifted out on so. the maximum operating clock frequency for fast read command is 133 mhz. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. figure 9.29 fast read (fast_read) command sequence (3-byte address, 0bh [cr2v[7]=0) note: 1. a = msb of address = 23 for cr2v[7]=0, or 31 for cr2v[7]=1 or command 0ch. 9.4.3 dual i/o read (d ior bbh or 4dior bch) the instruction ? bbh (cr2v[7] = 0) is followed by a 3-byte address (a23?a0) or ? bbh (cr2v[7] = 1) is followed by a 4-byte address (a31?a0) or ? bch is followed by a 4-byte address (a31?a0) the dual i/o read commands improve throughput with two i/o signal s ? io0 (si) and io1 (so). this command takes input of the address and returns read data two bits per sck rising edge. in some applications, the reduced address input and data output tim e might allow for code execution in place (xip) i.e. directly from the memory device. the maximum operating clock frequency for dual i/o read is 133 mhz. the dual i/o read command has continuous read mode bits that fo llow the address so, a series of dual i/o read commands may eliminate the 8-bit instruction after the first dual i/o read co mmand sends a mode bit pattern of axh that indicates the follow ing command will also be a dual i/o read command. the first dual i/ o read command in a series starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, fo llowed by an optional latency period. if the mode bit pattern is a xh the cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data n cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
document number: 002-00368 rev. *j page 98 of 151 S25FS128S s25fs256s next command is assumed to be an additional dual i/o read comma nd that does not provide instruct ion bits. that command starts with address, followed by mode bits, followed by optional latency. variable latency may be added after the mode bits are shifted into si and so before data begins shifting out of io0 and io1. th is latency period (dummy cycles) allows the de vice internal circuitry enough time to a ccess data at the initia l address. during th e dummy cycles, the data value on si and so are ?don?t care? and may be high imp edance. the number of dummy cycles is determined by the frequency of sck. the latency is configured in cr2v[3:0]. the continuous read feature removes the need for the instruction bits in a sequence of read accesses and greatly improves code execution (xip) performance. the upper nibble (bits 7-4) of the mode bits control the le ngth of the next dual i/o read command through the inclusion or exclusion of the fi rst byte instruction code. the lower nibble (bits 3-0) of the mode bits are ?don?t care? (?x?) and may be high impedance. if the mode bits equal axh, then the device remains in dual i/o continuous read mode and the next address can be entered (after cs# is raised high and then asse rted low) without the bbh or bc h instruction, as shown in figure 9.31 on page 99 ; thus, eliminating eight cycles of the command sequence. the following sequences will release the device from dual i/o continuous read mode; after which, th e device can accept standard spi commands: 1. during the dual i/o continuous read command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be rel eased from dual i/o con ti no us read mode. 2. send the mode reset command. note that the four mode bit cycles are part of the device?s in ternal circuitry latency time to access the initial address after the last address cycle that is clocke d into io0 (si) and io1 (so). it is important that the i/o signals be set to high-impedance at or before the falling edge of t he first data out clock. at hig her clock speeds the time available to turn off the host outputs before th e memory device begins to drive (b us turn around) is diminished . it is allowed and may be helpful in preventing i/o signal contention, for the host system to turn of f the i/o signal outputs (make th em high impedance) during the last two ?don?t care? mode cycles or during any dummy cycles. following the latency period the memory conten t, at the address given, is shifted out two bits at a time through io0 (si) and i o1 (so). two bits are shifted out at the sck frequency at the falling edge of sck signal. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. figure 9.30 dual i/o read command sequence (bbh) note: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command bbh. 2. a = msb of address = 31 with command bbh 3. least significant 4 bits of mode are don?t care and it is op tional for the host to drive thes e bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 a-1 2 0 6 4 2 0 6 4 2 0 6 4 2 0 a 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2
document number: 002-00368 rev. *j page 99 of 151 S25FS128S s25fs256s figure 9.31 dual i/o continuous read command sequen ce (4-byte addres s [cr2v[7] = 1]) note: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command bbh. 2. a = msb of address = 31 with command bbh 9.4.4 quad i/o read (q ior ebh or 4qior ech) the instruction ? ebh (cr2v[7] = 0) is followed by a 3-byte address (a23?a0) or ? ebh (cr2v[7] = 1) is followed by a 4-byte address (a31?a0) or ? ech is followed by a 4-byte address (a31?a0) the quad i/o read command improves throughput with four i/o signa ls ? io0?io3. it allows input of the address bits four bits pe r serial sck clock. in some applications, the reduced instruction overhea d might allow for code execution (xip) directly from s25 fs-s family devices. the quad bit of the configuration register must be set (cr1v[1] = 1) to enable the quad capability of s25fs-s family devices. the maximum operating clock frequency for quad i/o read is 133 mhz. for the quad i/o read command, there is a latency required after the m ode bits (described below) before data begins shifting ou t of io0-io3. this latency period (i.e., dummy cycles) allows the de vice?s internal circuitry enough time to access data at the init ial address. during latency cycles, the data value on io0?io3 ar e ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck. the latency is configured in cr2v[3:0]. following the latency period, the memory co ntents at the address given, is shifted out four bits at a time through io0?io3. eac h nibble (4 bits) is shifted out at the sck fr equency by the falling edge of the sck signal. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. address jumps can be done without the need for additional quad i/o read instructions. this is controlled through the setting of the mode bits (after the address sequence, as shown in figure 9.32, quad i/o read command sequence (ebh or ech) on page 100 ). this added feature removes the need for the instruction sequence and greatly improves code execution (xip). the upper nibble (b its 7-4) of the mode bits control the length of the next quad i/o in struction through the inclusion or exclusion of the first byte instruction code. the lower nibble (bits 3-0) of the mode bits are ?don?t ca re? (?x?). if the mode bits equal axh, then the device remains in quad i/o high performance read mode and the next address can be enter ed (after cs# is raised high and then asserted low) without requiring the ebh or ech instruction, as shown in figure 9.34, continuous quad i/o read command sequence (ebh or ech) on page 100 ; thus, eliminating eight cycles for the command sequence. the following sequences will release the device from quad i/o high performance read mode; after which, th e device can accept standard spi commands: 1. during the quad i/o read command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from quad i/o high performance read mode. 2. send the mode reset command. note that the two mode bit clock cycles an d additional wait states (i.e., dummy cycles) allow the device?s internal circuitry l atency time to access the initial addr ess after the last address cycle that is clocked into io0?io3. it is important that the io0?io3 signals be set to high-impedance at or before the falling edge of the first data out clock. at higher clock speeds the time available to turn off the host outputs befo re the memory device begins to drive (bus turn around) is dimi nished. cs# sck io0 io1 phase 6 4 2 0 a-1 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 a 3 1 7 5 3 1 7 5 3 1 7 5 3 1 data n address mode dum data 1 data 2
document number: 002-00368 rev. *j page 100 of 151 S25FS128S s25fs256s it is allowed and may be hel pful in preventing io0?io 3 signal contention, for the host system to turn off the io0?io3 signal ou tputs (make them high impedance) during the last ?don ?t care? mode cycle or during any dummy cycles. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. in qpi mode (cr2v[6] = 1) the quad i/o inst ructions are sent 4 bits per sck rising edge. the remainder of the command protocol i s identical to the quad i/o commands. figure 9.32 quad i/o read command sequence (ebh or ech) notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command ebh. 2. a = msb of address = 31 with command ech. figure 9.33 quad i/o read command sequence (ebh or ech), qpi mode notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command ebh. 2. a = msb of address = 31 with command ech. figure 9.34 continuous quad i/o read command sequence (ebh or ech) notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command ebh. 2. a = msb of address = 31 with command ech. cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 a-3 4 0 4 0 4 0 4 0 4 0 4 0 a-2 5 1 5 1 5 1 5 1 5 1 5 1 a-1 6 2 6 0 6 2 6 2 6 2 6 2 a 7 3 7 1 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 a-3 4 0 4 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 0 6 2 6 2 6 2 6 2 7 3 a 7 3 7 1 7 3 7 3 7 3 7 3 instruct. address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 4 0 a-3 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 a-2 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 a-1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 a 7 3 7 3 7 3 7 3 7 3 7 3 dn-1 dn address mode dummy d1 d2 d3 d4
document number: 002-00368 rev. *j page 101 of 151 S25FS128S s25fs256s 9.4.5 ddr quad i/o read (edh, eeh) the ddr quad i/o read command improves throughput with four i/ o signals - io0?io3. it is sim ilar to the quad i/o read command but allows input of the address four bits on every edge of the clock. in some applic ations, the reduced instruction overhead mi ght allow for code execution (xip) directly from s25fs-s family devi ces. the quad bit of the confi guration register must be set (cr1v[1] = 1) to enable the quad capability. the instruction ? edh (cr2v[7] = 0) is followed by a 3-byte address (a23?a0) or ? edh (cr2v[7] = 1) is followed by a 4-byte address (a31?a0) or ? eeh is followed by a 4-byte address (a31?a0) the address is followed by mode bits. then the memory contents, at the address given, is shifted out, in a ddr fashion, with fo ur bits at a time on each clock edge through io0?io3. the maximum operating clock frequency for ddr quad i/o read command is 80 mhz. for ddr quad i/o read, there is a latency required after the last address and mode bits are shifted into the io0-io3 signals be fore data begins shifting out of io0?io3. this latency pe riod (dummy cycles) allows the device?s internal circuitry enough time to a ccess the initial address. during these latency cycles, the data value on io0-io3 are ?don?t care? and may be high impedance. when th e data learning pattern (dlp) is enabled the host system must not drive the io signals during the dummy cycles. the io signals mu st be left high impedance by the host so that the memory device can dr ive the dlp during the dummy cycles. the number of dummy cycles is determined by the fre quency of sck. the latency is configured in cr2v[3:0]. mode bits allow a series of quad i/o ddr commands to elim inate the 8-bit instruction af ter the first command sends a complementary mode bit pattern, as shown in figure 9.35, ddr quad i/o read initial access (edh or eeh) on page 102 . this feature removes the need for the 8-bit sdr instruction sequence and dramatically r educes initial access times (improves xip performance). the mode bits cont rol the length of the next ddr quad i/o read oper ation through the inclusion or exclusion of th e first byte instruction code. if the upper nibble (io[7:4]) and lo wer nibble (io[3:0]) of the mode bits are complementary (i.e. 5h and ah) the device transitions to continuous ddr quad i/o read mode and the next address can be entered (after cs# is raised high and then asserted low) without requiring the edh or eeh instruction, as shown in figure 9.36, continuous ddr quad i/o read subsequent access (edh or eeh) on page 102 , thus eliminating eight cycles from the command sequence. the following sequences will release the device from continuous ddr quad i/o re ad mode; after which, the device can accept standard spi commands: 1. during the ddr quad i/o read command sequence, if the mode bits are not complementary the next time cs# is raised high and then asserted low the device will be released from ddr quad i/o read mode. 2. send the mode reset command. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bits as this may make the mode bits indete rminate. note that the memory devices may drive the ios with a preamble prior to the first data value. the preamble is a data learning pattern (dlp) that is used by the host controller to optimize data capture at higher frequencies. the preamble drives the io bus for the four clock cycles immediately before data is output. the host must be sure to stop driving the io bus prior to th e time that the memory starts outputting the preamble. the preamble is intended to give the host controller an indicati on about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. the host controller will skew the data capture point during t he preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read operation. the optimized capture point wil l be determined during the preamble period of every read operation. this optimization strategy is intended to compensate for both the pvt (process, vo ltage, temperature) of both t he memory device and the host controller as well as any system level delays caused by flight time on the pcb. although the data learning pattern (dlp) is programmable, t he following example shows example of the dlp of 34h. the dlp 34h (or 00110100) will be driven on each of the active outputs (i.e. a ll four sios). this pattern was chosen to cover both ?dc? and ?ac? data transition scenarios. the two dc transition scenarios include data low for a long period of time (two half clocks) followe d by a high going transition (001) and the complementary low going tran sition (110). the two ac transition scenarios include data low for a
document number: 002-00368 rev. *j page 102 of 151 S25FS128S s25fs256s short period of time (one half clock) followed by a high going transition (101) and the comple mentary low going transition (010 ). the dc transitions will typically occur with a starting point closer to the supply rail than the ac transitions that may not have f ully settled to their steady state (dc) levels. in many cases the dc trans itions will bound the beginning of the data valid period and the a c transitions will bound the ending of the data valid period. thes e transitions will allow the host controller to identify the be ginning and ending of the valid data eye. once the data eye has been ch aracterized the optimal data capture point can be chosen. see spi ddr data learning registers on page 65 for more details. in qpi mode (cr2v[6] = 1) the ddr quad i/o instructions are sent 4 bits per sck rising edge. the remainder of the command protocol is identical to the ddr quad i/o commands. figure 9.35 ddr quad i/o read initial access (edh or eeh) notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command edh. 2. a = msb of address = 31 with command eeh. figure 9.36 continuous ddr quad i/o read subsequent access (edh or eeh) notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command edh. 2. a = msb of address = 31 with command eeh. figure 9.37 ddr quad i/o read initial access (edh or eeh), qpi mode notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command edh. 2. a = msb of address = 31 with command eeh. cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 a-1 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 a 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address mode dummy dlp d1 d2 a-2 a-2 cs# sck io0 io1 io2 io3 phase a-3 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 a-2 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 a-1 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 a 15 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 address mode dummy d1 d2 d3 d4 d5 cs# sck io0 io1 io2 io3 phase 4 0 a-3 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 5 1 a-2 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 6 2 a-1 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 7 3 a 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruct. address mode dummy dlp d1 d2
document number: 002-00368 rev. *j page 103 of 151 S25FS128S s25fs256s 9.5 program flash array commands 9.5.1 program granularity 9.5.1.1 automatic ecc each 16 byte aligned and 16 byte length programming block has an automatic error correction code (ecc) value. the data block plus ecc form an ecc unit. in combination with error detection a nd correction (edc) logic the ecc is used to detect and correct any single bit error found during a read access. when data is fi rst programmed within an ecc unit the ecc value is set for the entire ecc unit. if the same ecc unit is programmed more than once the ecc value is changed to disable the edc function. a sector erase is needed to again enable automatic ecc on that programmi ng block. the 16 byte program block is the smallest program granularity on which automatic ecc is enabled. these are automatic operations transparent to the user. the transparency of the au tomatic ecc feature enhances data accuracy for typical programming operations which write data once to ea ch ecc unit but, facilitates software compatibility to previous generations of fl family of products by still allowing for single byte programming and bit walking in which the same ecc unit i s programmed more than once. when an ecc unit has automatic ecc disabled, edc is not done on data read from the ecc unit location. an ecc status register is provided for determining if ecc is en abled on an ecc unit and whether any errors have been detected and corrected in the ecc unit data or the ecc. the ecc status register read (eccrd) command is used to read the ecc status on any ecc unit. error detection and correction (edc) is applied to all parts of the flash address spaces other than registers. an error correct ion code (ecc) is calculated for each group of byte s protected and the ecc is st ored in a hidden area related to the group of bytes . the group of protected bytes and the relate d ecc are together called an ecc unit. ? ecc is calculated for each 16 byte aligned and length ecc unit ? single bit edc is supported with 8 ecc bits per ecc unit, plus 1 bit for an ecc disable flag ? sector erase resets all ecc disable flags in a sector to the default state (enabled) ? ecc is programmed as part of th e standard program commands operation ? ecc is disabled automatically if multiple progra mming operations are done on the same ecc unit. ? single byte programming or bit walking is allowed but disabl es ecc on the second program to the same 16 byte ecc unit. ? the ecc disable flag is programmed when ecc is disabled ? to re-enable ecc for an ecc unit that has been disabled, the sector that includes the ecc unit must be erased ? to ensure the best data integrity provided by edc, each ecc unit should be programmed only once so that ecc is stored for that unit and not disabled. ? the calculation, programming, and disablin g of ecc is done automatically as part of programming operations. the detection and correction if needed is done automatically as part of read op erations. the host system sees on ly corrected data from a read operation. ? ecc protects the otp region ? however a second program oper ation on the same ecc unit will disable ecc permanently on that ecc unit (otp is one time programmable, hence an erase oper ation to re-enable the ecc enable/indicator bit is prohibited) 9.5.1.2 page programming page programming is done by loading a page buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory array. this sets an upper limit on the amount of data that can be programmed with a single programming command. page programming allows up to a page size (either 256 or 512 bytes) to be programmed in one operation. the page size is determined by the configuration register bit cr3v[4]. the page is aligned on the page size address boundary. i t is possible to program from one bit up to a page size in each page pr ogramming operation. it is recommended that a multiple of 16- byte length and aligned program blocks be written. this insures that automatic ecc is not disabled. for the very best performan ce, programming should be done in full pages of 512 bytes aligned on 512-byte boundaries with each page being programmed only once.
document number: 002-00368 rev. *j page 104 of 151 S25FS128S s25fs256s 9.5.1.3 single byte programming single byte programming allows full back ward compatibility to the legacy standard spi page programming (pp) command by allowing a single byte to be programmed anywhere in the memory array. while single byte programming is supported, this will disable automatic ecc on the 16 byte ecc unit where the byte is located. 9.5.2 page program ( pp 02h or 4pp 12h) the page program (pp) command allows bytes to be programmed in the memory (changing bits from 1 to 0). before the page program (pp) commands can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device sets the write enable latch (wel) in the status register to e nable any write operations. the instruction ? 02h (cr2v[7] = 0) is followed by a 3-byte address (a23?a0) or ? 02h (cr2v[7] = 1) is followed by a 4-byte address (a31?a0) or ? 12h is followed by a 4-byte address (a31?a0) and at least one data byte on si. depending on cr3v[4], the page size can either be 256 or 512 bytes. up to a page can be provided on si after the 3-byte address with instruction 02h or 4-byte address with instruction 12h has been provided. if more data is sent to the device than the space between the starting address and the page aligned end boundary, the data load ing sequence will wrap from the last byte in the page to the zero byte location of the same page and begin overwriting any data previously loaded in the page. the last page worth of data is programmed in the page. this is a result of the device being equi pped with a page program buffer that is only page size in length. if less than a page of data is sent to the device, these data byte s will be programmed in sequence, starting at the provided address within the page, without having any affect on the other bytes of the s ame page. using the page program (pp) command to load an entire page , within the page boundary, will save overall programming time versus loading less than a page into the program buffer. the programming process is managed by the flash memory device internal control logic. after a programming command is issued, the programming operation status can be checked using the read status register 1 command. the wip bit (sr1v[0]) will indicate when the programming operation is completed. the p_err bit (sr1 v[6]) will indicate if an error occurs in the programming operation that prevents successful completion of programming. this includes attempted progr amming of a protected area. figure 9.38 page program (pp 02h or 4pp 12h) command sequence note: 1. a = msb of address = a23 for pp 02h, or a31 for 4pp 12h. this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. cs# sck si so phase 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2
document number: 002-00368 rev. *j page 105 of 151 S25FS128S s25fs256s figure 9.39 page program (pp 02h or 4pp 12h) qpi mode command sequence note: 1. a = msb of address = a23 for pp 02h, or a31 for 4pp 12h. 9.6 erase flash array commands 9.6.1 parameter 4-kb sector erase (p4e 20h or 4p4e 21h) the main flash array address map may be configured to overlay 4-kb parameter sectors over the lowest address portion of the lowest address uniform sector (bottom parame ter sectors) or over the highest address po rtion of the highest address uniform sec tor (top parameter sectors). the main flash array address map may also be configured to have only uniform size sectors. the parameter sector configuration is controlled by the configurat ion bit cr3v[3]. the p4e and 4p4e commands are ignored when the device is configured for unif orm sectors only (cr3v[3] = 1). the parameter 4-kb sector erase commands set all the bits of a 4-kb parameter sector to 1 (all bytes are ffh). before the p4e o r 4p4e command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enab le any write operations. the instruction ? 20h [cr2v[7] = 0] is followed by a 3-byte address (a23?a0), or ? 20h [cr2v[7] = 1] is followed by a 4-byte address (a31?a0), or ? 21h is followed by a 4-byte address (a31?a0) cs# must be driven into the logic high st ate after the twenty-fourth or thirty-second bit of the address has been latched in on si. this will initiate the beginnin g of internal erase cycle, which in volves the pre-programming and eras e of the chosen sector of the f lash memory array. if cs# is not driven high after the last bi t of address, the sector erase operation will not be executed. as soon as cs# is driven high, the internal erase cycle will be initiated. with the internal erase cycle in progress, the user can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1. when the erase cycle is in pr ogress and a 0 when the eras e cycle has been completed. a p4e or 4p4e command applied to a sector that has been write pr otected through the block protec tion bits or asp, will not be executed and will set the e_err status. a p4e command applied to a sector that is lar ger than 4 kbytes will not be executed and will not set the e_err status. figure 9.40 parameter sector erase (p4e 20h or 4p4e 21h) command sequence note: 1. a = msb of address = a23 for p4e 20h with cr2v[7] = 0, or a31 for p4e 20h with cr2v[7] = 1 or 4p4e 21h. this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. cs# sck io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 7 3 7 3 instruct. address input d1 input d2 input d3 input d4 cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address
document number: 002-00368 rev. *j page 106 of 151 S25FS128S s25fs256s figure 9.41 parameter sector erase (p4e 20h or 4p4e 21h) qpi mode command sequence note: 1. a = msb of address = a23 for p4e 20h with cr2v[7] = 0, or a31 for p4e 20h with cr2v[7] = 1 or 4p4e 21h. 9.6.2 sector erase ( se d8h or 4se dch) the sector erase (se) command sets all bits in the addressed se ctor to 1 (all bytes are ffh). before the sector erase (se) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? d8h [cr2v[7] = 0] is followed by a 3-byte address (a23?a0), or ? d8h [cr2v[7] = 1] is followed by a 4-byte address (a31?a0), or ? dch is followed by a 4-byte address (a31?a0) cs# must be driven into the logic high stat e after the twenty-fourth or thirty-second bit of address has been latched in on si. this will initiate the erase cycle, which in volves the pre-programm ing and erase of the chosen sector . if cs# is not driven high after th e last bit of address, the sector eras e operation will not be executed. as soon as cs# is driven into the logic high state, the internal erase cycle will be in itiated. with the internal erase cycle i n progress, the user can read the value of the write- in progress (wip) bit to check if the operation has been completed. the wip bit will i ndicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed. a sector erase (se) command applied to a se ctor that has been write prot ected through the block prot ection bits or asp, will no t be executed and will set the e_err status. a device configuration option (cr3v[1]) dete rmines whether the se command erases 64 kb ytes or 256 kbytes. the option to use this command to always erase 256 kbytes provides for software co mpatibility with higher density a nd future s25fs family devices. a device configuration option (cr3v[ 3]) determines whether 4-kb para meter sectors are in use. when cr3v[3] = 0, 4-kb parameter sectors overlay a portion of the highest or lowest address 32 kb of the device address space. if a sector erase command is appli ed to a 64-kb sector that is overlaid by 4-kb sectors, the overlaid 4-kb sectors are no t affected by the erase. only the visible ( non- overlaid) portion of the 64-kb sector appears erased. similarly if a sector erase command is applied to a 256-kb range that is overlaid by 4-kb sectors, the overlaid 4- kb sectors are not affected by the erase. when cr3v[3] = 1, there are no 4-kb paramete r sectors in the device address space and th e sector erase command always operates on fully visible 64-kb or 256-kb sectors. asp has a ppb and a dyb protection bit for each physical sector, includ ing any 4-kb sectors. if a sector erase command is appli ed to a 256-kb range that includes a 64-kb protected physical sect or, the erase will not be executed on the 256-kb range and will set the e_err status. cs# sck io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address
document number: 002-00368 rev. *j page 107 of 151 S25FS128S s25fs256s figure 9.42 sector erase (se d8h or 4se dch) command sequence note: 1. a = msb of address = a23 for se d8h with cr2v[7] = 0, or a31 for se d8h with cr2v[7] = 1 or 4p4e dch. this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0-io3, two clock cycles per byte. figure 9.43 sector erase (se d8h or 4se dch) qpi mode command sequence note: 1. a = msb of address = a23 for p4e 20h with cr2v[7] = 0, or a31 for p4e 20h with cr2v[7] = 1 or 4p4e 21h. 9.6.3 bulk erase (be 60h or c7h) the bulk erase (be) command sets all bits to 1 (all bytes are ff h) inside the entire flash memory array. before the be command can be accepted by the device, a write enable (wren) command must be issued an d decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has been latched in on si. this will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory array. if cs# is not driven high after the last bit of instruction, the be ope ration will not be executed. as soon as cs# is driven into the logic high state, the erase cycle will be initiate d. with the erase cycle in progress, the us er can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1 when the erase cycle is in pr ogress and a 0 when the eras e cycle has been completed. a be command can be executed only when the block protection (bp2, bp1, bp0) bits are set to 0s. if the bp bits are not 0, the b e command is not executed and e_err is not set. the be comma nd will skip any sectors protected by the dyb or ppb and the e_err status will not be set. figure 9.44 bulk erase command sequence this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address cs# sck io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00368 rev. *j page 108 of 151 S25FS128S s25fs256s figure 9.45 bulk erase command sequence qpi mode 9.6.4 evaluate erase status (ees d0h) the evaluate erase status (ees) command verifies that the last erase operati on on the addressed sector was completed successfully. if the selected sect or was successfully erased the erase status bit (sr2v[2]) is set to 1. if the sele cted sector was not completely erased sr2v[2] is 0. the ees command can be us ed to detect erase operations failed due to loss of power, reset, or fail ure during the erase operatio n. the ees instruction is followed by a 3- or 4-byte address, de pending on the address length co nfiguration (cr2v[7]). the ees command requires t ees to complete and update the erase status in sr2v . the wip bit (sr1v[0]) may be read using the rdsr1 (05h) command, to determine when the ees command is finish ed. then the rdsr2 (07h) or the rdar (65h) command can be used to read sr2v[2]. if a sector is found not erased with sr2v[2] = 0, the sector must be erased again to ensure reliable stor age of data in the sector. the write enable command (to set the wel bi t) is not required before th e ees command. however, the we l bit is set by the device itself and cleared at the end of the operation, as visible in sr1v[1] when reading status. figure 9.46 ees command sequence note: 1. a = msb of address = a23 for cr2v[7] = 0, or a31 for cr2v[7] = 1. this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. figure 9.47 ees qpi mode command sequence note: 1. a = msb of address = a23 for cr2v[7] = 0, or a31 for cr2v[7] = 1. cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address cs# sck io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address
document number: 002-00368 rev. *j page 109 of 151 S25FS128S s25fs256s 9.6.5 program or erase su spend (pes 85h, 75h, b0h) there are three instruction codes for program or erase suspend (pes) to enable legacy and alternate source software compatibili ty. the pes command allows the system to interrupt a programming or erase operation and then r ead from any other non-erase- suspended sector or non-program-suspended-page . program or erase suspend is valid only during a programming or sector erase operation. a bulk erase operation cannot be suspended. the write-in-progress (wip) bit in status register 1 (sr1v[0]) must be checked to know when the programming or erase operation has stopped. the program suspend status bi t in the status register 2 (sr2[0]) ca n be used to determine if a programming operation has been suspended or was complete d at the time wip changes to 0. the eras e suspend status bit in the status register 2 (sr2[1]) can be used to determine if an erase operation has been suspended or was comple ted at the time wip changes to 0. the time required for the suspend operation to complete is t sl , see program or erase suspend ac parameters on page 122 . an erase can be suspended to allow a program operation or a read operation. during an erase suspend, the dyb array may be read to examine sector protection and written to remove or restore protection on a sector to be programmed. a program operation may be suspende d to allow a read operation. a new erase operation is not allowed with an already suspended eras e or program operation. an erase command is ignored in this situation. commands allowed during program or erase suspend (sheet 1 of 2) instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment pp 02 x required for array program during erase suspend. only allowed if there is no other program suspended program operation (sr2v[0]=0). a program command will be ignored while there is a suspended program. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. read 03 x x all array reads allowed in suspend. rdsr1 05 x x needed to read wip to determine end of suspend process. rdar 65 x x alternate way to read wip to determine end of suspend process. wren 06 x required for program command within erase suspend. rdsr2 07 x x needed to read suspend status to determine whether the operation is suspended or complete. 4pp 12 x required for array program during erase suspend. only allowed if there is no other program suspended program operation (sr2v[0] = 0). a program command will be ignored while there is a suspended program. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. 4read 13 x x all array reads allowed in suspend. clsr 30 x clear status may be used if a program operation fails during erase suspend. note the instruction is only valid if enabled for clear status by cr4nv[2] = 1. clsr 82 x clear status may be used if a program operation fails during erase suspend. epr 30 x x required to resume from erase or program suspend. note the command must be enabled for use as a resume command by cr4nv[2] = 0. epr 7a x x required to resume from erase or program suspend. epr 8a x x required to resume from erase or program suspend. rsten 66 x x reset allowed anytime. rst 99 x x reset allowed anytime. fast_read 0b x x all array reads allowed in suspend. 4fast_read 0c x x all array reads allowed in suspend. epr 7a x required to resume from erase suspend. epr 8a x required to resume from erase suspend. dior bb x x all array reads allowed in suspend. 4dior bc x x all array reads allowed in suspend.
document number: 002-00368 rev. *j page 110 of 151 S25FS128S s25fs256s reading at any address within an erase-suspended sector or program-suspended page produces undetermined data. the wrr, wrar, or ppb erase commands are not allowed during eras e or program suspend, it is therefore not possible to alter the block protection or ppb bits during erase suspend. if ther e are sectors that may need pr ogramming during erase suspend, these sectors should be pr otected only by dyb bits that can be turned off during erase suspend. after an erase-suspended program operation is complete, the device returns to the erase-suspend mode. the system can determine the status of the program operati on by reading the wip bit in the status r egister, just as in the standard program operation. figure 9.48 program or erase suspend command sequence figure 9.49 program or erase suspend command sequence this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. dybrd fa x it may be necessary to remove and re store dynamic protection during erase suspend to allow programming during erase suspend. dybwr fb x it may be necessary to remove and re store dynamic protection during erase suspend to allow programming during erase suspend. ppbrd fc x allowed for checking persistent pr otection before attempting a program command during erase suspend. 4dybrd e0 x it may be necessary to remove and re store dynamic protection during erase suspend to allow programming during erase suspend. 4dybwr e1 x it may be necessary to remove and re store dynamic protection during erase suspend to allow programming during erase suspend. 4ppbrd e2 x allowed for checking persistent pr otection before attempting a program command during erase suspend. qior eb x x all array reads allowed in suspend. 4qior ec x x all array reads allowed in suspend. ddrqior ed x x all array reads allowed in suspend. 4ddrqior ee x x all array reads allowed in suspend. reset f0 x x reset allowed anytime. mbr ff x x may need to reset a read operation during suspend. commands allowed during program or erase suspend (sheet 2 of 2) instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment cs# sck si so phase phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 suspend instruction read status instruction status instr. during suspend repeat status read until suspended tsl cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00368 rev. *j page 111 of 151 S25FS128S s25fs256s figure 9.50 program or erase suspend command sequence qpi mode 9.6.6 erase or program resu me (epr 7ah, 8ah, 30h) there are three instruction codes for erase or program resume (epr) to enable legacy and alternate source software compatibilit y. after program or read operations are completed during a program or erase suspend the erase or program resume command is sent to continue the suspended operation. after an erase or program resume command is issued, the wip bit in the status register 1 will be set to a 1 and the programming operation will resume if one is suspended. if no program operation is suspended the susp ended erase operation will resume. if t here is no suspended program or erase operation the resume command is ignored. program or erase operations may be interr upted as often as necessary e.g. a progra m suspend command could immediately follow a program resume command but, in order for a program or erase op eration to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t rs . see program or erase suspend ac parameters on page 122 . an erase or program resume command must be written to resume a suspended operation. figure 9.51 erase or program resume command sequence figure 9.52 erase or program resume command sequence qpi mode 9.7 one-time program array commands 9.7.1 otp program (otpp 42h) the otp program command programs data in the one-time program region, which is in a different address space from the main array data. the otp region is 1024 bytes so, the address bits from a31 to a10 must be 0 for this command. refer to otp address space on page 49 for details on the otp region. cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
document number: 002-00368 rev. *j page 112 of 151 S25FS128S s25fs256s before the otp program command can be a ccepted by the device, a write enable (w ren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the wip bit in sr 1v may be checked to determine when the operation is completed. the p_err bit in sr1v may be checked to determine if any error occurred during the operation. to program the otp array in bit granularity, the rest of the bits within a data byte can be set to 1. each region in the otp memory space can be programmed one or more times, provided that the region is not locked. attempting to program 0s in a region that is locked will fail with the p_err bi t in sr1v set to 1. programming ones, even in a protected area does not cause an error and does not set p_err. subsequent otp prog ramming can be performed only on the un-programmed bits (that is, 1 data). programming more than once within an ecc unit will disable ecc on that unit. the protocol of the otp program command is the same as the page program command. see page program (pp 02h or 4pp 12h) on page 104 for the command sequence. 9.7.2 otp read (otpr 4bh) the otp read command reads data from the otp region. the otp regi on is 1024 bytes so, the address bits from a31 to a10 must be zero for this command. refer to otp address space on page 49 for details on the otp region. the protocol of the otp read command is similar to the fast read command except that it will not wrap to the starting address after the otp address is at it s maximum; instead, the data beyo nd the maximum otp address will be undefined. the otp read command read latency is set by the latency value in cr2v[3:0]. see fast read (fast_read 0bh or 4fast_read 0ch) on page 97 for the command sequence. 9.8 advanced sector protection commands 9.8.1 asp read (asprd 2bh) the asp read instruction 2bh is shifted into si by the rising edg e of the sck signal. then the 16-bit asp regist er contents are shifted out on the serial output so, least significant byte firs t. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the asp re gister continuously by prov iding multiples of 16 clo ck cycles. the maximum operati ng clock frequency for the asp read (asprd) command is 133 mhz. figure 9.53 asprd command 9.8.2 asp program (aspp 2fh) before the asp program (aspp) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the aspp command is entered by driv ing cs# to the logic low state, followed by the instruction and two data bytes on si, least significant byte first. the asp regist er is two data bytes in length. the aspp command affects the p_err and wip bits of the status and configuration registers in the same manner as any other programming operation. cs# input must be driven to the logic high state after the sixteenth bit of data has been latched in. if not, the aspp command is not executed. as soon as cs# is driven to the logic high state, the self-timed aspp operation is initiated. while the aspp operatio n is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction output aspr low byte output aspr high byte
document number: 002-00368 rev. *j page 113 of 151 S25FS128S s25fs256s 1 during the self-timed aspp operation, and is a 0 when it is completed. when the aspp operation is complet ed, the write enable latch (wel) is set to a 0. figure 9.54 aspp command 9.8.3 dyb read (dyb rd fah or 4dybrd e0h) the instruction is latched into si by the rising edge of the sck signal. the instruction is followed by the 24 or 32-bit addres s, depending on the address length configuration cr2v[7], selecting location zero within the desired sector. note, the high order address bits not used by a particular density device must be ze ro. then the 8-bit dyb access register contents are shifted out on the serial output so. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read th e same dyb access register continuously by provid ing multiples of eight clock cycles. the add ress of the dyb register does not increme nt so this is not a means to read the entire dyb array. each location must be re ad with a separate dyb read command. the maximum operating clock frequency for read command is 133 mhz. figure 9.55 dybrd command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7] = 1 with command fah. 2. a = msb of address = 31 with command e0h. this command is also supported in qpi mode. in qpi mode the in struction and address is shifted in on io0?io3 and returning data is shifted out on io0?io3. figure 9.56 dybrd qpi mode command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7] = 1 with command fah. 2. a = msb of address = 31 with command e0h. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input aspr low byte input aspr high byte cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address register repeat register cs# sck io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 5 1 a-2 5 1 5 1 6 2 a-1 6 2 6 2 7 3 a 7 3 7 3 instruction address output dybar
document number: 002-00368 rev. *j page 114 of 151 S25FS128S s25fs256s 9.8.4 dyb write (dybwr fbh or 4dybwr e1h) before the dyb write (dybwr) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the dybwr command is entered by driving cs# to the logic low stat e, followed by the instruction, followed by the 24- or 32-bit address, depending on the address length c onfiguration cr2v[7], selecting location zero within the desired sector (note, the hi gh order address bits not used by a particular density device must be zero ), then the data byte on si. the dyb access register is one data byte in length. the data value must be 00h to protect or ffh to unprotect the selected sector. the dybwr command affects the p_err and wip bits of the status and configuration re gisters in the same manner as any other programming operation. cs# must be driven to the logic high stat e after the eighth bit of data has been latched in. as soon as cs# is driven to the logic high state, the se lf-timed dybwr operation is in itiated. while the dybwr operation is in progress, the s tatus register may be read to check the value of the write-in progre ss (wip) bit. the write-in progress (wip) bit is a 1 during the s elf- timed dybwr operation, and is a 0 when it is completed. when the dybwr operation is completed, the write enable latch (wel) is set to a 0. figure 9.57 dybwr command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7] = 1 with command fbh. 2. a = msb of address = 31 with command e1h. this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. figure 9.58 dybwr qpi mode command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7] = 1 with command fbh. 2. a = msb of address = 31 with command e1h 9.8.5 ppb read (ppb rd fch or 4ppbrd e2h) the instruction e2h is shifted into si by the rising edges of the sck signal, followed by the 24- or 32-bit address, depending on the address length configuration cr2v[7], selecting location zero wit hin the desired sector (note, the high order address bits not used by a particular density device must be zero). then the 8-bit ppb access regist er contents are shifted out on so. it is possible to read the same ppb access re gister continuously by providing multiple s of eight clock cycles. the address of t he ppb register does not increment so this is not a means to read the entire ppb array. each location must be read with a separate ppb read command. the maximum operating clock frequency for the ppb read command is 133 mhz. cs# sck si so phase 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data cs# sck io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 5 1 a-2 5 1 5 1 6 2 a-1 6 2 6 2 7 3 a 7 3 7 3 instruction address input dybar
document number: 002-00368 rev. *j page 115 of 151 S25FS128S s25fs256s figure 9.59 ppbrd command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7] = 1 with command fch. 2. a = msb of address = 31 with command e2h. 9.8.6 ppb program (ppb p fdh or 4ppbp e3h) before the ppb program (ppbp) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the ppbp command is entered by driv ing cs# to the logic low state, followed by the instruction, follow ed by the 24- or 32-bit address, depending on the address length c onfiguration cr2v[7], selecting location zero within the desired sector (note, the hi gh order address bits not used by a parti cular density device must be zero). the ppbp command affects the p_err and wip bits of the status and configuration registers in the same manner as any other programming operation. cs# must be driven to the logic high stat e after the last bit of address has been latched in. if not, the ppbp command is not executed. as soon as cs# is driven to the logic high state, the self-timed ppbp operation is initiated. while the ppbp operatio n is in progress, the status register ma y be read to check the value of the write-in progress (wip) bit. the wip bit is a 1 during the self- timed ppbp operation, and is a 0 when it is completed. when th e ppbp operation is completed, the write enable latch (wel) is se t to a 0. figure 9.60 ppbp command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7] = 1 with command fdh. 2. a = msb of address = 31 with command e3h. 9.8.7 ppb erase (ppbe e4h) the ppb erase (ppbe) command sets all ppb bits to 1. before the ppb erase command can be ac cepted by the device, a write enable (wren) command must be issued and decoded by the devi ce, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction e4h is shifted into si by the rising edges of the sck signal. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has been latched in on si. this will initiate the beginning of internal erase cycl e, which involves the pre-prog ramming and erase of the entire ppb memory array. without cs# being driven to the logic high state after the eighth bit of the instruction, the ppb eras e operation will not be executed. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address register repeat register cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address
document number: 002-00368 rev. *j page 116 of 151 S25FS128S s25fs256s with the internal erase cycle in progress, the user can read th e value of the write- in progress (wip) bit to check if the opera tion has been completed. the wip bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been complet ed. erase suspend is not allowed during ppb erase. figure 9.61 ppb erase command sequence 9.8.8 ppb lock bit read (plbrd a7h) the ppb lock bit read (plbrd) command allows the ppb lock register contents to be read out of so. it is possible to read the ppb lock register continuously by providing multiples of eight clock cycles. the ppb lo ck register contents may only be read wh en the device is in standby state with no other operation in progress. it is recommended to check the write-in progress (wip) bit of the status register before issui ng a new command to the device. figure 9.62 ppb lock register read command sequence 9.8.9 ppb lock bit write (plbwr a6h) the ppb lock bit write (plbwr) co mmand clears the ppb lock regist er to zero. before the pl bwr command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, whic h sets the write enable latch (wel) in the status register to enable any write operations. the plbwr command is entered by driving cs# to the logic low state, followed by the instruction. cs# must be driven to the logic high state after the eighth bit of instruction has b een latched in. if not, the plbwr command i s not executed. as soon as cs# is dr iven to the logic high state, th e self-timed plbwr operation is initiated. while the plbwr operat ion is in progress, the status register may st ill be read to check the value of the writ e-in progress (wip) bit. the write-in progr ess (wip) bit is a 1 during the self-timed plbwr op eration, and is a 0 when it is complete d. when the plbwr o peration is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the plbwr command is 133 mhz. figure 9.63 ppb lock bit write command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00368 rev. *j page 117 of 151 S25FS128S s25fs256s 9.8.10 password r ead (passrd e7h) the correct password value may be read only after it is pr ogrammed and before the password mode has been selected by programming the password protection mode bi t to 0 in the asp register (a sp[2]). after the password pr otection mode is selected the password is no longer readable, th e passrd command will output undefined data. the passrd command is shifted into si. then th e 64-bit password is shifted out on the serial output so, least significant byte first, most significant bit of each byte first. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the password continuously by pr oviding multiples of 64 cloc k cycles. the maximum operati ng clock frequency for the passrd command is 133 mhz. figure 9.64 password read command sequence 9.8.11 password pr ogram (passp e8h) before the password program (passp) comma nd can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded, the device sets the write enable latch (wel) to enabl e the passp operation. the password can only be programmed before the password mode is selected by programming th e password protection mode bit to 0 in the asp register (asp[2]). af ter the password protection mode is se lected the passp command is ignored. the passp command is entered by driving cs# to the logic low stat e, followed by the instruction and the password data bytes on si, least significant byte first, most signi ficant bit of each byte first. the passwo rd is sixty-four (64) bits in length. cs# must be driven to the logic hi gh state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passp command is not executed. as soon as cs# is driven to the logic high state, the se lf-timed passp operation is init iated. while the passp operat ion is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a 1 during the self-timed passp cycle, and is a 0 when it is complet ed. the passp command can repo rt a program error in the p_err bit of the status register. when the passp operation is co mpleted, the write enable latch (wel) is set to a 0. the maximum clock frequency for the passp command is 133 mhz. figure 9.65 password program command sequence 9.8.12 password unlock (passu e9h) the passu command is entered by driving cs# to the logic low st ate, followed by the instruction and the pa ssword data bytes on si, least significant byte first, most signi ficant bit of each byte first. the passwo rd is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passu command is not executed. as soon as cs# is driven to the logic high state, the self-timed passu oper ation is initiated. while the passu operat ion cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input password low byte input password high byte
document number: 002-00368 rev. *j page 118 of 151 S25FS128S s25fs256s is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a 1 during the self-timed passu cycle, and is a 0 when it is completed. if the passu command supplied password does not match the hidden password in the password register, an error is reported by setting the p_err bit to 1. the wip bit of the status register al so remains set to 1. it is nece ssary to use the clsr command t o clear the status register, the reset comma nd to software reset the device, or drive the reset# in put low to initiate a hardware reset, in order to return the p_err and wip bits to 0. this returns the device to standby state, ready for new commands such as a retry of the passu command. if the password does match, the ppb lock bi t is set to 1. the maximum clock fr equency for the passu command is 133 mhz. figure 9.66 password unlock command sequence 9.9 reset commands software controlled reset commands restore the device to its init ial power-up state, by reloadin g volatile registers from non-v olatile default values. however, the vo latile freeze bit in th e configuration register cr1v[0] and the volati le ppb lock bit in the ppb lock register are not changed by a software reset. the software reset cannot be used to circumvent the freeze or ppb lock bit protection mechanisms for the other security configuration bits. the freeze bit and the ppb lock bit will remain set at their la st value prior to the software reset. to clear the freeze bit an d set the ppb lock bit to its protection mode selected power-on state, a full power-on-reset sequence or hardware reset must be done. the non-volatile bits in the c onfiguration register (cr1nv), tb prot_o, tbparm, and bpn v_o, retain their pr evious state after a software reset. the block protection bits bp2, bp1, and bp0, in the status regist er (sr1v) will only be reset to their default value if freeze = 0. a reset command (rst or reset) is executed when cs# is brought high at the end of the instruction and requires t rph time to execute. in the case of a previous power-up reset (por) failure to complete, a reset command triggers a full power-up sequence requiring t pu to complete. figure 9.67 software reset command sequence this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input password low byte input password high byte cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00368 rev. *j page 119 of 151 S25FS128S s25fs256s figure 9.68 software reset command sequence qpi mode 9.9.1 software reset enable (rsten 66h) the reset enable (rsten) command is required immediately befor e a reset command (rst) such that a software reset is a sequence of the two commands. any command other than rst foll owing the rsten command, will clear the reset enable condition and prevent a later rst command from being recognized. 9.9.2 software reset (rst 99h) the reset (rst) command immediately following a rsten command, initiates the so ftware reset process. 9.9.3 legacy software reset (reset f0h) the legacy software reset (reset) is a single command that initia tes the software reset process. this command is disabled by default but can be enabled by programming cr3v[0] = 1, fo r software compatibility with cypress legacy fl-s devices. 9.9.4 mode bit reset (mbr ffh) the mode bit reset (mbr) command is used to return the device from continuous high performance read mode back to normal standby awaiting any new command. becaus e some device packages la ck a hardware reset# input a nd a device that is in a continuous high performance read mode may not recognize any norma l spi command, a system hardwa re reset or so ftware reset command may not be recognized by the device. it is recomme nded to use the mbr command after a system reset when the reset# signal is not available or, before sending a software rese t, to ensure the device is released from continuous high performance read mode. the mbr command sends 1s on si or io0 for 8 sck cycl es. io1 to io3 are ?don?t care? during these cycles. figure 9.69 mode bit reset command sequence this command is also supported in qpi mode. in qpi mode the in struction is shifted in on io0?io3, two clock cycles per byte. cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00368 rev. *j page 120 of 151 S25FS128S s25fs256s figure 9.70 mode bit reset command sequence qpi mode 9.10 dpd commands 9.10.1 enter deep power-down (dpd b9h) although the standby current during normal o peration is relatively low, standby current can be further reduced with the deep po wer down command. the lower power consumption makes the deep power-down (dpd) command especially useful for battery powered applications (see i dpd in section 4.6, dc characteristics on page 26 ). the dpd command is accepted only while the device is not performi ng an embedded operation as indi cated by the status register- 1 volatile write in progress (wip) bit being cleared to zero (sr1v[0] = 0). the command is initiated by driving the cs# pin low and shifting the instruction code ?b9h? as shown in figure 9.71, deep power- down command sequence . the cs# pin must be driven high after the eighth bi t has been latched. if this is not done, the deep power-down command will not be executed. afte r cs# is driven high, the power-down st ate will be entered within the time duratio n of t dpd (see section 5., timing specifications on page 27 ). while in the power-down state, only the release from deep powe r-down command, which restores the device to normal operation, will be recognized. all other commands are ignored. this includes the read status register command, which is always available during normal operation. ignoring all but one command also make s the power down state useful for write protection. the device always powers-up in the interface standby state with the standby current of i cc1 . figure 9.71 deep power-down command sequence this command is also supported in qpi mode. in qpi mode, the in struction is shifted in on io0?i o3, two clock cycles per byte. figure 9.72 dpd command sequence qpi mode cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
document number: 002-00368 rev. *j page 121 of 151 S25FS128S s25fs256s 9.10.2 release from deep power-down (res abh) the release from deep power-down command is used to release the device from the deep power-d own state. in some legacy spi devices, the res command could also be used to obtain the devic e electronic identificat ion (id) number. however, the device id function is not supported by the res command. to release the device from the deep power-down state, the command is issued by driving the cs# pin low, shifting the instructio n code ?abh? and driving cs# high as shown in figure 9.73, release from deep power-down command sequence . release from deep power-down will take the time duration of t res (see section 5., timing specifications on page 27 ) before the device will resume normal operation and other commands are acc epted. the cs# pin must remain high during the t res time duration. hardware reset will also release the device from th e dpd state as part of the hardware reset process. figure 9.73 release from deep power-down command sequence this command is also supported in qpi mode. in qpi mode, the in struction is shifted in on io0?i o3, two clock cycles per byte. figure 9.74 res command sequence qpi mode cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
document number: 002-00368 rev. *j page 122 of 151 S25FS128S s25fs256s 10. embedded algorith m performance tables the joint electron device engineering council (jedec) standard j esd22-a117 defines the procedural requirements for performing valid endurance and retention tests based on a qualification specification. this methodology is intended to determine the abili ty of a flash device to sustain repeated data changes without failure (progr am/erase endurance) and to retain data for the expected lif e (data retention). endurance and retention qualification specif ications are specified in jesd47 or may be developed using knowledge-based methods as in jesd94. notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25 c, v cc = 1.8 v; random data pattern. 3. the programming time for any otp programming command is the same as t pp . this includes otpp 42h, pnvdlr 43h, aspp 2fh, and passp e8h. 4. the programming time for the ppbp e3h command is the same as t pp . the erase time for ppbe e4h command is the same as t se . 5. data retention of 20 years is based on 1k erase cycles or less. program and erase performance symbol parameter min typ (2) max unit t w non-volatile register write time 240 750 ms t pp page programming (512 bytes) page programming (256 bytes) 475 360 2000 2000 s t se sector erase time (64-kb or 4-kb physical sectors) 240 725 ms sector erase time (256-kb logical sectors = 4x64k physical sectors) 930 2900 ms t be (1) bulk erase time (S25FS128S) 60 180 sec t be (1) bulk erase time (s25fs256s) 120 360 sec t ees evaluate erase status time (64-kb or 4-kb physical sectors) 20 25 s evaluate erase status time (256-kb physical or logical sectors) 80 100 erase per sector 100,000 cycles program or erase suspend ac parameters parameter typical max unit comments suspend latency (t sl ) 50 s the time from suspend command until the wip bit is 0. resume to next program suspend (t rs ) 100 s minimum is the time needed to issue the next suspend command but typical periods are needed for program or erase to progress to completion.
document number: 002-00368 rev. *j page 123 of 151 S25FS128S s25fs256s 11. data integrity 11.1 erase endurance note: 1. each write command to a non-volatile register causes a p/e cycl e on the entire non-volatile register array. otp bits and regi sters internally reside in a separate array that is not p/e cycled. 11.2 data retention contact cypress sales or an fae represent ative for additional information on data inte grity. an application note is available a t: http://www.cypre ss.com/appnotes . 11.3 serial flash discoverable parameters (sfdp) address map the sfdp address space has a header starting at address zero that identifies the sfdp data stru cture and provides a pointer to each parameter. one basic flash parameter is mandated by the jedec jesd216b standard. two optional parameter tables for sector map and 4-byte address instructions follow the basic flas h table. cypress provides an additional parameter by pointing t o the id-cfi address space i.e. the id-cfi address space is a sub- set of the sfdp address space. the parameter tables portion of the sfdp data structure are located within the id -cfi address space and is thus both a cfi parameter and an sfdp parameter. in this way both sfdp and id-cfi information can be accessed by either the rsfdp or rdid commands. table 11.1 erase endurance parameter minimum unit program/erase cycles per main fl ash array sectors 100k p/e cycle program/erase cycles per ppb array or non-volatile register array (1) 100k p/e cycle table 11.2 data retention parameter test conditions minimum time unit data retention time 10k program/erase cycles 20 years 100k program/erase cycles 2 years sfdp overview map byte address description 0000h location zero within jedec jesd216b sfdp space ? start of sfdp header. ,,, remainder of sfdp header followed by undefined space. 1000h location zero within id-cfi space ? start of id-cfi parameter tables. ... id-cfi parameters. 1090h start of sfdp parameter tables which are also grouped as on e of the cfi parameter tables (the cfi parameter itself starts at 108eh, the sfdp parameter table data is double word aligned starting at 1090h). ... remainder of sfdp parameter tables followed by either more cfi parameters or undefined space.
document number: 002-00368 rev. *j page 124 of 151 S25FS128S s25fs256s 11.3.1 field definitions sfdp header (sheet 1 of 2) sfdp byte address sfdp dword name data description 00h sfdp header 1st dword 53h this is the entry point for read sfdp (5ah) command i.e. location zero within sfdp space ascii ?s? 01h 46h ascii ?f? 02h 44h ascii ?d? 03h 50h ascii ?p? 04h sfdp header 2nd dword 06h sfdp minor revision (06h = jedec jesd216 revision b) this revision is backward compatible with all prior minor revisions. minor revisions are changes that define previously reserved fields , add fields to the end, or that clarify definitions of existing fields. increments of the minor revision value indicate that previously reserved parameter fields may have been assigned a new definition or entire dwords may have been added to the parameter table. however, the definition of previously existing fields is unchanged and therefore remain backward compatible with earlier sfdp parameter table revisions. software can safely ignore increments of the minor revision number, as long as only those parameters the software was designed to support are used i.e. previ ously reserved fields and additional dwords must be masked or ignored. do not do a simple compare on the minor revision number, looking only for a match with the revision number that the software is designed to handle. there is no problem with using a higher number minor revision. 05h 01h sfdp major revision this is the original major revision. this major revision is compatible with all sfdp reading and parsing software. 06h 05h number of parameter headers (zero based, 05h = 6 parameters) 07h ffh unused 08h parameter header 0 1st dword 00h parameter id lsb (00h = jedec sfdp basic spi flash parameter) 09h 00h parameter minor revision (00h = jesd216) - this older revision parameter header is provided for any legacy sfdp reading and parsing software that requires seeing a minor revision 0 parameter header. sfdp software designed to handle later minor revisions should continue reading parameter headers looking for a higher numbered minor revision that contains additional parameters for that software revision. 0ah 01h parameter major revision (01h = the original major revision - all sfdp software is compatible with this major revision. 0bh 09h parameter table length (in double words = dwords = 4 byte units) 09h = 9 dwords 0ch parameter header 0 2nd dword 90h parameter table pointer byte 0 (dword = 4 byte aligned) jedec basic spi flash parameter byte offset = 1090h 0dh 10h parameter table pointer byte 1 0eh 00h parameter table pointer byte 2 0fh ffh parameter id msb (ffh = jedec defined legacy parameter id) 10h parameter header 1 1st dword 00h parameter id lsb (00h = jedec sfdp basic spi flash parameter) 11h 05h parameter minor revision (05h = jesd216 revision a) - this older revision parameter header is provided for any legacy sfdp reading and parsing software that requires seeing a minor revision 5 parameter header. sfdp software designed to handle later minor revisions should continue reading parameter headers looking for a later minor revision that contains additional parameters. 12h 01h parameter major revision (01h = the original major revision - all sfdp software is compatible with this major revision. 13h 10h parameter table length (in double words = dwords = 4 byte units) 10h = 16 dwords 14h parameter header 1 2nd dword 90h parameter table pointer byte 0 (dword = 4 byte aligned) jedec basic spi flash parameter byte offset = 1090h address 15h 10h parameter table pointer byte 1 16h 00h parameter table pointer byte 2 17h ffh parameter id msb (ffh = jedec defined parameter)
document number: 002-00368 rev. *j page 125 of 151 S25FS128S s25fs256s 18h parameter header 2 1st dword 00h parameter id lsb (00h = jedec sfdp basic spi flash parameter) 19h 06h parameter minor revision (06h = jesd216 revision b) 1ah 01h parameter major revision (01h = the original major revision - all sfdp software is compatible with this major revision. 1bh 10h parameter table length (in double words = dwords = 4 byte units) 10h = 16 dwords 1ch parameter header 2 2nd dword 90h parameter table pointer byte 0 (dword = 4 byte aligned) jedec basic spi flash parameter byte offset = 1090h address 1dh 10h parameter table pointer byte 1 1eh 00h parameter table pointer byte 2 1fh ffh parameter id msb (ffh = jedec defined parameter) 20h parameter header 3 1st dword 81h parameter id lsb (81h = sfdp sector map parameter) 21h 00h parameter minor revision (00h = initia l version as defined in jesd216 revision b) 22h 01h parameter major revision (01h = the original major revision - all sfdp software that recognizes this parameter?s id is compatible with this major revision. 23h 1ah (128mb) 1ah (256mb) parameter table length (in double words = dwords = 4 byte units) opn dependent 26 = 1ah (128mb) 26 = 1ah (256mb) 24h parameter header 3 2nd dword d8h parameter table pointer byte 0 (dword = 4 byte aligned) jedec parameter byte offset = 10d8h 25h 10h parameter table pointer byte 1 26h 00h parameter table pointer byte 2 27h ffh parameter id msb (ffh = jedec defined parameter) 28h parameter header 4 1st dword 84h parameter id lsb (00h = sfdp 4 byte address instructions parameter) 29h 00h parameter minor revision (00h = initia l version as defined in jesd216 revision b) 2ah 01h parameter major revision (01h = the original major revision - all sfdp software that recognizes this parameter?s id is compatible with this major revision. 2bh 02h parameter table length (in double words = dwords = 4 byte units) (2h = 2 dwords) 2ch parameter header 4 2nd dword d0h parameter table pointer byte 0 (dword = 4 byte aligned) jedec parameter byte offset = 10d0h 2dh 10h parameter table pointer byte 1 2eh 00h parameter table pointer byte 2 2fh ffh parameter id msb (ffh = jedec defined parameter) 30h parameter header 5 1st dword 01h parameter id lsb (cypress vendor specific id-cfi parameter) legacy manufacturer id 01h = amd / cypress 31h 01h parameter minor revision (01h = id-cfi updated with sfdp rev b table) 32h 01h parameter major revision (01h = the original major revision - all sfdp software that recognizes this parameter?s id is compatible with this major revision. 33h 50h (128mb) 50h (256mb) parameter table length (in double words = dwords = 4 byte units) parameter table length (in double words = dwords = 4 byte units) cfi starts at 1000h, the final sfdp parameter (cfi id = a5) starts at 111eh (sfdp starting point of 1090h -2hb of cfi parameter header), for a length of 8ehb excluding the cfi a5 parameter. the final cfi a5 parameter for 128mb adds an additional b2hb for a total of 8eh + b2h = 140hb. 140hb/4 = 50h dwords the final cfi a5 parameter for 256mb adds an additional b2hb for a total of 8eh + b2h = 140hb. 140hb/4 = 50h dwords 34h parameter header 5 2nd dword 00h parameter table pointer byte 0 (dword = 4 byte aligned) entry point for id-cfi parameter is byte offset = 1000h relative to sfdp location zero. 35h 10h parameter table pointer byte 1 36h 00h parameter table pointer byte 2 37h 01h parameter id msb (01h = jedec jep106 bank number 1) sfdp header (sheet 2 of 2) sfdp byte address sfdp dword name data description
document number: 002-00368 rev. *j page 126 of 151 S25FS128S s25fs256s 11.4 device id and common flash interface (id-cfi) address map 11.4.1 field definitions manufacturer and device id byte address data description 00h 01h manufacturer id for cypress 01h 20h (128 mb) 02h (256 mb) device id most significant byte - memory interface type 02h 18h (128 mb) 19h (256 mb) device id least significant byte - density 03h 4dh id-cfi length - number bytes following. adding this value to the current location of 03h gives the address of the last valid location in the id-cfi legacy address map. the legacy cfi address map ends with the primary vendor-specific extended query. the original legacy length is maintained for backward software compatibility. however, the cfi query identification string also includes a pointer to the alternate vendor-specific extended query that contains additional information related to the fs-s family. 04h 00h (uniform 256-kb physical sectors) 01h (uniform 64-kb physical sectors) physical sector architecture the s25fs-s family may be configured with or without 4-kb parameter sectors in addition to the uniform sectors. 05h 81h (s25fs-s family) family id 06h xxh ascii characters for model refer to ordering information on page 144 for the model number definitions. 07h xxh 08h xxh reserved 09h xxh reserved 0ah xxh reserved 0bh xxh reserved 0ch xxh reserved 0dh xxh reserved 0eh xxh reserved 0fh xxh reserved cfi query identification string byte address data description 10h 11h 12h 51h 52h 59h query unique ascii string ?qry? 13h 14h 02h 00h primary oem command set fl-p backward compatible command set id 15h 16h 40h 00h address for primary extended table 17h 18h 53h 46h alternate oem command set ascii characters ?fs? for spi (f) interface, s technology 19h 1ah 51h 00h address for alternate oem extended table
document number: 002-00368 rev. *j page 127 of 151 S25FS128S s25fs256s cfi system interface string byte address data description 1bh 17h v cc min. (erase/program): 100 millivolts bcd 1ch 19h v cc max. (erase/program): 100 millivolts bcd 1dh 00h v pp min. voltage (00h = no v pp present) 1eh 00h v pp max. voltage (00h = no v pp present) 1fh 09h typical timeout per single byte program 2 n s 20h 09h typical timeout for min. size page program 2 n s (00h = not supported) 21h 08h (4 kb or 64 kb) 0ah (256 kb) typical timeout per individual sector erase 2 n ms 22h 10h (128 mb) 11h (256 mb) typical timeout for full chip erase 2 n ms (00h = not supported) 23h 02h max. timeout for byte program 2 n times typical 24h 02h max. timeout for page program 2 n times typical 25h 05h (4 kb or 64 kb) 04h (256 kb) max. timeout per individual sector erase 2 n times typical 26h 03h max. timeout for full chip erase 2 n times typical (00h = not supported)
document number: 002-00368 rev. *j page 128 of 151 S25FS128S s25fs256s note: 1. fs-s devices are user configur able to have either a hybrid sector architecture (with eight 4-kb sectors and all remaining sec tors are uniform 64 kb or 256 kb) or a uniform sector architecture with all sectors uniform 64 kb or 256 kb. fs-s devices are also user configurable to have the 4-kb parameter sectors at the top of memory address space. the cfi geometry information of the above table is relevant only to the initial delivery state. all devices are initially shipped from cypress with the hybrid sector architecture with the 4-kb sectors located at the bottom of the array address map. however, the device configurat ion tbparm bit cr1nv[2] may be programed to invert the sector map to place the 4-kb sectors at the top of the array address map. the 20h_nv bit (cr3nv[3} may be programmed to remove the 4-kb sectors from the address map. the flash device driver software must examine the tbparm and 20h_nv bits to determine if the sect or map was inverted or hybrid sectors removed at a later time. device geometry definition for bottom boot initial delivery state byte address data description 27h 18h (128 mb) 19h (256 mb) device size = 2 n bytes 28h 02h flash device interface description; 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = single i/o spi, 3-byte address 0005h = multi i/o spi, 3-byte address 0102h = multi i/o spi, 3- or 4-byte address 29h 01h 2ah 08h max. number of bytes in multi-byte write = 2 n 0000 = not supported 0008h = 256b page 2bh 00h 2ch 03h number of erase block regions within device 1 = uniform device, >1 = boot device 2dh 07h erase block region 1 information (refer to jedec jep137) 8 sectors = 8-1 = 0007h 4-kb sectors = 256 bytes x 0010h 2eh 00h 2fh 10h 30h 00h 31h 00h erase block region 2 information (refer to jedec jep137) 128 mb and 256 mb: 1 sector = 1-1 = 0000h 32-kb sector = 256 bytes x 0080h 32h 00h 33h 80h 34h 00h (128 mb) 00h (256 mb) 35h feh erase block region 3 information 128 mb and 256 mb: 255 sectors = 255-1 = 00feh (128 mb) 511 sectors = 511-1 = 01feh (256 mb) 64-kb sectors = 0100h x 256 bytes 36h 00h (128 mb) 01h (256 mb) 37h 00h 38h 01h (128 mb) 01h (256 mb) 39h thru 3fh ffh rfu
document number: 002-00368 rev. *j page 129 of 151 S25FS128S s25fs256s the alternate vendor-specific extended query provides informati on related to the expanded command set provided by the fs-s family. the alternate query parameters use a format in which ea ch parameter begins with an ident ifier byte and a parameter leng th byte. driver software can check each parameter id and can use t he length value to skip to the next parameter if the parameter i s not needed or not recognized by the software. cfi primary vendor-specific extended query byte address data description 40h 50h query-unique ascii string ?pri? 41h 52h 42h 49h 43h 31h major version number = 1, ascii 44h 33h minor version number = 3, ascii 45h 21h address sensitive unlock (bits 1-0) 00b = required, 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.11 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 1000b = 0.065 m mirrorbit 46h 02h erase suspend 0 = not supported 1 = read only 2 = read and program 47h 01h sector protect 00 = not supported x = number of sectors in group 48h 00h temporary sector unprotect 00 = not supported 01 = supported 49h 08h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method 4ah 00h simultaneous operation 00 = not supported x = number of sectors 4bh 01h burst mode (synchronous sequential read) support 00 = not supported 01 = supported 4ch 03h page mode type, initial delivery configuration, user configurable for 512b page 00 = not supported 01 = 4 word read page 02 = 8-read word page 03 = 256-byte program page 04 = 512-byte program page 4dh 00h acc (acceleration) supply minimum 00 = not supported, 100 mv 4eh 00h acc (acceleration) supply maximum 00 = not supported, 100 mv 4fh 07h wp# protection 01 = whole chip 04 = uniform device with bottom wp protect 05 = uniform device with top wp protect 07 = uniform device with top or bottom write protect (user configurable) 50h 01h program suspend 00 = not supported 01 = supported
document number: 002-00368 rev. *j page 130 of 151 S25FS128S s25fs256s cfi alternate vendor-specific extended query header byte address data description 51h 41h query-unique ascii string ?alt? 52h 4ch 53h 54h 54h 32h major version number = 2, ascii 55h 30h minor version number = 0, ascii cfi alternate vendor-specifi c extended query parameter 0 parameter relative byte address offset data description 00h 00h parameter id (ordering part number) 01h 10h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 53h ascii ?s? for manufacturer (cypress) 03h 32h ascii ?25? for product characters (single die spi) 04h 35h 05h 46h ascii ?fs? for interface characters (spi 1.8 volt) 06h 53h 07h 31h (128 mb) 32h (256 mb) ascii characters for density 08h 32h (128 mb) 35h (256 mb) 09h 38h (128 mb) 36h (256 mb) 0ah 53h ascii ?s? for technology (65 nm mirrorbit) 0bh ffh reserved for future use 0ch ffh 0dh ffh reserved for future use 0eh ffh 0fh ffh reserved for future use 10h xxh ascii characters for model refer to ordering information on page 144 for the model number definitions. 11h xxh cfi alternate vendor-specific extended query parameter 80h address options parameter relative byte address offset data description 00h 80h parameter id (ordering part number) 01h 01h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h ebh bits 7:5 - reserved = 111b bit 4 - address length bit in cr2v[7] - yes = 0b bit 3 - autoboot support - no = 1b bit 2 - 4 byte address instructions supported - yes = 0b bit 1 - bank address + 3-byte address instructions supported - no = 1b bit 0 - 3-byte address instructions supported - no = 1b
document number: 002-00368 rev. *j page 131 of 151 S25FS128S s25fs256s cfi alternate vendor-specific extended query parameter 84h suspend commands parameter relative byte address offset data description 00h 84h parameter id (suspend commands) 01h 08h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 75h program suspend instruction code 03h 28h program suspend latency maximum (s) 04h 7ah program resume instruction code 05h 64h program resume to next suspend typical (s) 06h 75h erase suspend instruction code 07h 28h erase suspend latency maximum (s) 08h 7ah erase resume instruction code 09h 64h erase resume to next suspend typical (s) cfi alternate vendor-spe cific extended query para meter 88h data protection parameter relative byte address offset data description 00h 88h parameter id (data protection) 01h 04h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 0ah otp size 2 n bytes, ffh = not supported 03h 01h otp address map format, 01h = fl-s and fs-s format ffh = not supported 04h xxh block protect type, model dependent 00h = fl-p, fl-s, fs-s ffh = not supported 05h xxh advanced sector protection type, model dependent 01h = fl-s and fs-s asp. cfi alternate vendor-specific extend ed query parameter 8ch reset timing parameter relative byte address offset data description 00h 8ch parameter id (reset timing) 01h 06h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 96h por maximum value 03h 01h por maximum exponent 2 n s 04h 23h hardware reset maximum value, ffh = not supported (the initial delivery state has hardware reset disabled but it may be enabled by the user at a later time) 05h 00h hardware reset maximum exponent 2 n s 06h 23h software reset maximum value, ffh = not supported 07h 00h software reset maximum exponent 2 n s
document number: 002-00368 rev. *j page 132 of 151 S25FS128S s25fs256s this parameter type (param eter id f0h) may appear multiple times and have a di fferent length each time. the parameter is used t o reserve space in the id-cfi map or to force space (pad) to align a following parameter to a required boundary. cfi alternate vendor-specific extended query parameter 94h ecc parameter relative byte address offset data description 00h 94h parameter id (ecc) 01h 01h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 10h ecc unit size byte, ffh = ecc disabled cfi alternate vendor-specific ex tended query parameter f0h rfu parameter relative byte address offset data description 00h f0h parameter id (rfu) 01h 09h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h ffh rfu ... ffh rfu 10h ffh rfu cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 1, basic flash parameter and 4 by te address instructions parameter (sheet 1 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp relative dword name data description 00h -- n/a a5h cfi parameter id (jedec sfdp) 01h -- n/a b0h (128mb) b0h (256mb) cfi parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter). opn dependent: 18dw + 26dw = 44dw *4b = 176b = b0h b (128mb) b0h (256mb) 02h 00h jedec basic flash parameter dword-1 e7h start of sfdp jedec parameter, located at 1090h in the overall sfdp address space. bits 7:5 = unused = 111b bit 4:3 = 06h is status register write instruction & status register is default non-volatile= 00b bit 2 = program buffer > 64bytes = 1 bits 1:0 = uniform 4kb erase unavailable = 11b 03h 01h ffh bits 15:8 = uniform 4kb erase opcode = not supported = ffh 04h 02h b2h (fsxxxsag) bit 23 = unused = 1b bit 22 = supports quad out read = no = 0b bit 21 = supports quad i/o read = yes =1b bit 20 = supports dual i/o read = yes = 1b bit19 = supports ddr 0= no, 1 = yes; fs-sag = 0b, fs-sds = 1b bit 18:17 = number of address bytes, 3 or 4 = 01b bit 16 = supports dual out read = no = 0b 05h 03h ffh bits 31:24 = unused = ffh
document number: 002-00368 rev. *j page 133 of 151 S25FS128S s25fs256s 06h 04h jedec basic flash parameter dword-2 ffh density in bits, zero based 07h 05h ffh 08h 06h ffh 09h 07h 07h (128mb) 0fh (256mb) 0ah 08h jedec basic flash parameter dword-3 48h bits 7:5 = number of quad i/o (1-4-4) mode cycles = 010b bits 4:0 = number of quad i/o dummy cycles = 01000b (initial delivery state) 0bh 09h ebh quad i/o instruction code 0ch 0ah ffh bits 23:21 = number of quad out (1-1-4) mode cycles = 111b bits 20:16 = number of quad out dummy cycles = 11111b 0dh 0bh ffh quad out instruction code 0eh 0ch jedec basic flash parameter dword-4 ffh bits 7:5 = number of dual out (1-1-2) mode cycles = 111b bits 4:0 = number of dual out dummy cycles = 11111b 0fh 0dh ffh dual out instruction code 10h 0eh 88h bits 23:21 = number of dual i/o (1-2-2) mode cycles = 100b bits 20:16 = number of dual i/o dummy cycles = 01000b (initial delivery state) 11h 0fh bbh dual i/o instruction code 12h 10h jedec basic flash parameter dword-5 feh bits 7:5 rfu = 111b bit 4 = qpi supported = yes = 1b bits 3:1 rfu = 111b bit 0 = dual all not supported = 0b 13h 11h ffh bits 15:8 = rfu = ffh 14h 12h ffh bits 23:16 = rfu = ffh 15h 13h ffh bits 31:24 = rfu = ffh 16h 14h jedec basic flash parameter dword-6 ffh bits 7:0 = rfu = ffh 17h 15h ffh bits 15:8 = rfu = ffh 18h 16h ffh bits 23:21 = number of dual all mode cycles = 111b bits 20:16 = number of dual all dummy cycles = 11111b 19h 17h ffh dual all instruction code 1ah 18h jedec basic flash parameter dword-7 ffh bits 7:0 = rfu = ffh 1bh 19h ffh bits 15:8 = rfu = ffh 1ch 1ah 48h bits 23:21 = number of qpi mode cycles = 010b bits 20:16 = number of qpi dummy cycles = 01000b 1dh 1bh ebh qpi mode quad i/o (4-4-4) instruction code 1eh 1ch jedec basic flash parameter dword-8 0ch erase type 1 size 2 n bytes = 4kb = 0ch for hybrid (initial delivery state) 1fh 1dh 20h erase type 1 instruction 20h 1eh 10h erase type 2 size 2 n bytes = 64kb = 10h 21h 1fh d8h erase type 2 instruction 22h 20h jedec basic flash parameter dword-9 12h erase type 3 size 2 n bytes = 256kb = 12h 23h 21h d8h erase type 3 instruction 24h 22h 00h erase type 4 size 2 n bytes = not supported = 00h 25h 23h ffh erase type 4 instruction = not supported = ffh cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 1, basic flash parameter and 4 by te address instructions parameter (sheet 2 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp relative dword name data description
document number: 002-00368 rev. *j page 134 of 151 S25FS128S s25fs256s 26h 24h jedec basic flash parameter dword-10 e2h bits 31:30 = erase type 4 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 1s = 11b (rfu) bits 29:25 = erase type 4 erase, typical time count = 11111b ( rfu) bits 24:23 = erase type 3 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 128ms = 10b bits 22:18 = erase type 3 erase, typical time count = 00111b (typ erase time = count +1 * units = 8*128ms = 930 ms) bits 17:16 = erase type 2 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 16ms = 01b bits 15:11 = erase type 2 erase, typical time count = 01110b (typ erase time = count +1 * units = 15*16ms = 240ms) bits 10:9 = erase type 1 erase, typi cal time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 16ms = 01b bits 8:4 = erase type 1 erase, typical time count = 01110b (typ erase time = count +1 * units = 15*16ms = 240ms) bits 3:0 = multiplier from typical erase time to maximum erase time = 2*(n+1), n=2h binary fields: 11-11111-10-00111-01-01110-01-01110-0010 nibble format: 1111_1111_0001_1101_0111_0010_1110_0010 hex format: ff_11_42_82 27h 25h 72h 28h 26h 1dh 29h 27h ffh 2ah 28h jedec basic flash parameter dword-11 91h bit 31 reserved = 1b bits 30:29 = chip erase, typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 128mb = 4s = 10b; 256mb = 4s = 10b bits 28:24 = chip erase, typical time count, (count+1)*units, 128mb = 4s = 01110b = 14+1*4 = 60s; 256mb = 11101 = 29+1*4 = 120s bits 23 = byte program typical time, additional byte units (0b:1us, 1b:8us) = 1us = 0b bits 22:19 = byte program typical time, additional byte count, (count+1)*units, count = 0000b, ( typ program time = count +1 * units = 1*1us = 1us bits 18 = byte program typical time, first byte units (0b:1us, 1b:8us) = 8us = 1b bits 17:14 = byte program typical time , first byte count, (count+1)*units, count = 1100b, ( typ program time = count +1 * units = 13*8us = 104us bits 13 = page program typical time units (0b:8us, 1b:64us) = 64us = 1b bits 12:8 = page program typical time count, (count+1)*units, count = 00110b, ( typ program time = count +1 * units = 7*64us = 448us) bits 7:4 = page size 2 n , n=9h, = 512b page bits 3:0 = multiplier from typical time to maximum for page or byte program = 2*(n+1), n=1h = 4x multiplier 128mb binary fields: 1-10-01110-0-0000-1-1100-1-00110-1001-0001 nibble format: 1100_1110_0000_0111_0010_0110_1001_0001 hex format: c7_07_26_91 256mb binary fields: 1-10-11101-0-0000-1-1100-1-00110-1001-0001 nibble format: 1101_1101_0000_0111_0010_0110_1001_0001 hex format: dd_07_26_91 2bh 29h 26h 2ch 2ah 07h 2dh 2bh c7h (128mb) ddh (256mb) cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 1, basic flash parameter and 4 by te address instructions parameter (sheet 3 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp relative dword name data description
document number: 002-00368 rev. *j page 135 of 151 S25FS128S s25fs256s 2eh 2ch jedec basic flash parameter dword-12 ech bit 31 = suspend and resume supported = 0b bits 30:29 = suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 8us= 10b bits 28:24 = suspend in-progress erase max latency count = 00100b, max erase suspend latency = count +1 * units = 5*8us = 40us bits 23:20 = erase resume to suspend interval count = 0001b, interval = count +1 * 64us = 2 * 64us = 128us bits 19:18 = suspend in-progress program max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 8us= 10b bits 17:13 = suspend in-progress program max latency count = 00100b, max erase suspend latency = count +1 * units = 5*8us = 40us bits 12:9 = program resume to suspend interval count = 0001b, interval = count +1 * 64us = 2 * 64us = 128us bit 8 = rfu = 1b bits 7:4 = prohibited operations during erase suspend = xxx0b: may not initiate a new erase anywhere (erase nesting not permitted) + xx1xb: may not initiate a page program in the erase suspended sector size + x1xxb: may not initiate a read in the erase suspended sector size + 1xxxb: the erase and program restrictions in bits 5:4 are sufficient = 1110b bits 3:0 = prohibited operations during program suspend = xxx0b: may not initiate a new erase anywhere (e rase nesting not permitted) + xx0xb: may not initiate a new page program anywhere (program nesting not permitted) + x1xxb: may not initiate a read in the program suspended page size + 1xxxb: the erase and program rest rictions in bits 1:0 are sufficient = 1100b binary fields: 0-10-00100-0001-10-00100-0001-1-1110-1100 nibble format: 0100_0100_0001_1000_1000_0011_1110_1100 hex format: 44_18_83_ec 2fh 2dh 83h 30h 2eh 18h 31h 2fh 44h 32h 30h jedec basic flash parameter dword-13 8ah bits 31:24 = erase suspend instruction = 75h bits 23:16 = erase resume instruction = 7ah bits 15:8 = program suspend instruction = 85h bits 7:0 = program resume instruction = 8ah 33h 31h 85h 34h 32h 7ah 35h 33h 75h 36h 34h jedec basic flash parameter dword-14 f7h bit 31 = deep power down supported = supported = 0 bits 30:23 = enter deep power down instruction = b9h bits 22:15 = exit deep power down instruction = abh bits 14:13 = exit deep power down to next operation delay units = (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 1us = 01b bits 12:8 = exit deep power down to next operation delay count = 11101b, exit deep power down to next operation delay = (count+1)*units = 29+1 *1us = 30us bits 7:4 = rfu = fh bit 3:2 = status register polling device busy = 01b: legacy status polling supported = use legacy polling by reading the status register with 05h instruction and checking wip bit[0] (0=ready; 1=busy). = 01b bits 1:0 = rfu = 11b binary fields: 0-10111001-10101011-01-11101-1111-01-11 nibble format: 0101_1100_1101_0101_1011_1101_ 1111_0111 hex format: 5c_d5_bd_f7 37h 35h bdh 38h 36h d5h 39h 37h 5ch cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 1, basic flash parameter and 4 by te address instructions parameter (sheet 4 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp relative dword name data description
document number: 002-00368 rev. *j page 136 of 151 S25FS128S s25fs256s 3ah 38h jedec basic flash parameter dword-15 8ch bits 31:24 = rfu = ffh bit 23 = hold and wp disable = not supported = 0b bits 22:20 = quad enable requirements = 101b: qe is bit 1 of the status register 2. status register 1 is read using read status instruction 05h. status register 2 is read using instruction 35h. qe is set via write status instruction 01h with two data bytes where bit 1 of the second byte is one. it is cleared via write status with two da ta bytes where bit 1 of the second byte is zero. bits 19:16 0-4-4 mode entry method = xxx1b: mode bits[7:0] = a5h note: qe must be set prior to using this mode + x1xxb: mode bit[7:0]=axh + 1xxxb: rfu = 1101b bits 15:10 0-4-4 mode exit method = xx_xxx1b: mode bits[7:0] = 00h will terminate this mode at the end of the current read operation + xx_1xxxb: input fh (mode bit reset) on dq0-dq3 for 8 clocks. this will terminate the mo de prior to the next r ead operation. + x1_xxxxb: mode bit[7:0] != axh + 1x_x1xx: rfu = 11_1101 bit 9 = 0-4-4 mode supported = 1 bits 8:4 = 4-4-4 mode enable sequ ences = x_1xxxb: dev ice uses a read- modify-write sequence of operations: read configuration using instruction 65h followed by address 800003h, set bit 6, write configuration using instruction 71h followed by address 800003h. this configuration is volatile. = 01000b bits 3:0 = 4-4-4 mode disable s equences = x1xxb: dev ice uses a read- modify-write sequence of operations: read configuration instruction 65h followed by address 800003h, clear bi t 6, write configuration using instruction 71h followed by address 800003h.. this configuration is volatile. + 1xxxb: issue the soft reset 66/99 sequence = 1100b binary fields: 11111111-0- 101-1101- 111101-1-01000-1100 nibble format: 1111_1111_0101_1101_1111_0110_1000-1100 hex format: ff_5d_f6_8c 3bh 39h f6h 3ch 3ah 5dh 3dh 3bh ffh 3eh 3ch jedec basic flash parameter dword-16 f0h bits 31:24 = enter 4-byte addressi ng = xxxx_xxx1b: issue instruction b7h (preceding write enable not required) + xx1x_xxxxb: supports dedicated 4- byte address instruction set. consult vendor data sheet for the instruction set definition. + 1xxx_xxxxb: reserved = 10100001b bits 23:14 = exit 4-byte addressing = xx_xx1x_xxxxb: hardware reset + xx_x1xx_xxxxb: software reset (see bits 13:8 in this dword) + xx_1xxx_xxxxb: power cycle + x1_xxxx_xxxxb: reserved + 1x_xxxx_xxxxb: reserved = 11_1110_0000b bits 13:8 = soft reset and rescue sequence support = x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. the reset enable, reset sequence may be issued on 1, 2, or 4 wires depending on the device operating mode. + 1x _xxxxb: exit 0-4-4 mode is required prior to other reset sequences above if the dev ice may be operating in this mode. = 110000b bit 7 = rfu = 1 bits 6:0 = volatile or non-volatile register and write enable instruction for status register 1 = + xx1_xxxxb: status register 1 contains a mix of volatile and non-volatile bits. the 06h instruction is used to enable writing of the register. + x1x_xxxxb: reserved + 1xx_xxxxb: reserved = 1110000b binary fields: 10100001- 11111 00000-110000-1-1110000 nibble format: 1010_0001_ 1111_1000_0011_0000_ 1111_0000 hex format: a1_f8_30_f0 3fh 3dh 30h 40h 3eh f8h 41h 3fh a1h cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 1, basic flash parameter and 4 by te address instructions parameter (sheet 5 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp relative dword name data description
document number: 002-00368 rev. *j page 137 of 151 S25FS128S s25fs256s 42h 40h jedec 4 byte address instructions parameter dword-1 6bh supported = 1, not supported = 0 bits 31:20 = rfu = fffh bit 19 = support for non-volatile individual sector lock write command, instruction=e3h = 1 bit 18 = support for non-volatile individual sector lock read command, instruction=e2h = 1 bit 17 = support for volatile individual sector lock write command, instruction=e1h = 1 bit 16 = support for volatile individual sector lock read command, instruction=e0h = 1 bit 15 = support for (1-4-4) dtr_read command, instruction = eeh = 1 bit 14 = support for (1-2-2) dtr_read command, instruction = beh = 0 bit 13 = support for (1-1-1) dtr_read command, instruction = 0eh = 0 bit 12 = support for erase command ? type 4 = 0 bit 11 = support for erase command ? type 3 = 1 bit 10 = support for erase command ? type 2 = 1 bit 9 = support for erase command ? type 1 = 1 bit 8 = support for (1-4-4) page program command, instruction = 3eh =0 bit 7 = support for (1-1-4) page program command, instruction = 34h = 0 bit 6 = support for (1-1-1) page program command, instruction = 12h = 1 bit 5 = support for (1-4-4) fast_read command, instruction = ech = 1 bit 4 = support for (1-1-4) fast_read command, instruction = 6ch = 0 bit 3 = support for (1-2-2) fast_read command, instruction = bch = 1 bit 2 = support for (1-1-2) fast_read command, instruction = 3ch = 0 bit 1 = support for (1-1-1) fast_read command, instruction = 0ch = 1 bit 0 = support for (1-1-1) read command, instruction=13h = 1 43h 41h 8eh 44h 42h ffh 45h 43h ffh 46h 44h jedec 4 byte address instructions parameter dword-2 21h bits 31:24 = ffh = instruction for erase type 4: rfu bits 23:16 = dch = instruction for erase type 3 bits 15:8 = dch = instruction for erase type 2 bits 7:0 = 21h = instruction for erase type 1 47h 45h dch 48h 46h dch 49h 47h ffh cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 2, sector map parameter table, 128mb and 256m b (sheet 1 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description 4ah 48h jedec sector map parameter dword-1 config. detect-1 fch bits 31:24 = read data mask = 0000_1000b: select bit 3 of the data byte for 20h_nv value 0= hybrid map with 4kb parameter sectors 1= uniform map bits 23:22 = configuration detection command address length = 11b: variable length bits 21:20 = rfu = 11b bits 19:16 = configuration detection command latency = 1111b: variable latency bits 15:8 = configuration detection instruction = 65h: read any register bits 7:2 = rfu = 111111b bit 1 = command descriptor = 0 bit 0 = not the end descriptor = 0 4bh 49h 65h 4ch 4ah ffh 4dh 4bh 08h cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 1, basic flash parameter and 4 by te address instructions parameter (sheet 6 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp relative dword name data description
document number: 002-00368 rev. *j page 138 of 151 S25FS128S s25fs256s 4eh 4ch jedec sector map parameter dword-2 config. detect-1 04h bits 31:0 = sector map configuration detection command address = 00_00_00_04h: address of cr3nv 4fh 4dh 00h 50h 4eh 00h 51h 4fh 00h 52h 50h jedec sector map parameter dword-3 config. detect-2 fch bits 31:24 = read data mask = 0000_0100b: select bit 2 of the data byte for tbparm_o value 0= 4kb parameter sectors at bottom 1= 4kb parameter sectors at top bits 23:22 = configuration detection command address length = 11b: variable length bits 21:20 = rfu = 11b bits 19:16 = configuration detection command latency = 1111b: variable latency bits 15:8 = configuration detection instruction = 65h: read any register bits 7:2 = rfu = 111111b bit 1 = command descriptor = 0 bit 0 = not the end descriptor = 0 53h 51h 65h 54h 52h ffh 55h 53h 04h 56h 54h jedec sector map parameter dword-4 config. detect-2 02h bits 31:0 = sector map configuration detection command address = 00_00_00_02h: address of cr1nv 57h 55h 00h 58h 56h 00h 59h 57h 00h 5ah 58h jedec sector map parameter dword-5 config. detect-3 fdh bits 31:24 = read data mask = 0000_0010b: select bit 1 of the data byte for d8h_nv value 0= 64kb uniform sectors 1= 256kb uniform sectors bits 23:22 = configuration detection command address length = 11b: variable length bits 21:20 = rfu = 11b bits 19:16 = configuration detection command latency = 1111b: variable latency bits 15:8 = configuration detection instruction = 65h: read any register bits 7:2 = rfu = 111111b bit 1 = command descriptor = 0 bit 0 = the end descriptor = 1 5bh 59h 65h 5ch 5ah ffh 5dh 5bh 02h 5eh 5ch jedec sector map parameter dword-6 config. detect-3 04h bits 31:0 = sector map configuration detection command address = 00_00_00_04h: address of cr3nv 5fh 5dh 00h 60h 5eh 00h 61h 5fh 00h 62h 60h jedec sector map parameter dword-7 config-0 header feh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 02h: three regions bits 15:8 = configuration id = 00h: 4kb sectors at bottom with remainder 64kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = not the end descriptor = 0 63h 61h 00h 64h 62h 02h 65h 63h ffh 66h 64h jedec sector map parameter dword-8 config-0 region-0 f1h bits 31:8 = region size = 00007fh: region size as count-1 of 256 byte units = 8 x 4kb sectors = 32kb count = 32kb/256 = 128, value = count -1 = 128 -1 = 127 = 7fh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 4kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 4kb sector region bit 0 = erase type 1 support = 1b ---erase type 1 is 4kb erase and is supported in the 4kb sector region 67h 65h 7fh 68h 66h 00h 69h 67h 00h cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 2, sector map parameter table, 128mb and 256m b (sheet 2 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description
document number: 002-00368 rev. *j page 139 of 151 S25FS128S s25fs256s 6ah 68h jedec sector map parameter dword-9 config-0 region-1 f2h bits 31:8 = region size = 00007fh: region size as count-1 of 256 byte units = 1 x 32kb sectors = 32kb count = 32kb/256 = 128, value = count -1 = 128 -1 = 127 = 7fh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 32kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 32kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 32kb sector region 6bh 69h 7fh 6ch 6ah 00h 6dh 6bh 00h 6eh 6ch jedec sector map parameter dword-10 config-0 region-2 f2h bits 31:8 = 128mb device region size = 00feffh: region size as count-1 of 256 byte units = 255 x 64kb sectors = 16320kb count = 16320kb/256 = 65280, value = count -1 = 65280 -1 = 65279 = feffh bits 31:8 = 256mb device region size = 01feffh: region size as count-1 of 256 byte units = 511 x 64kb sectors = 32704kb count = 32704kb/256 = 130816, value = count -1 = 130816 -1 = 130815 = 1feffh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 64kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 64kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 64kb sector region 6fh 6dh ffh 70h 6eh feh 71h 6fh 00h (128mb) 01h (256mb) 72h 70h jedec sector map parameter dword-11 config-2 header feh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 02h: three regions bits 15:8 = configuration id = 02h: 4kb sectors at top with remainder 64kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = not the end descriptor = 0 73h 71h 02h 74h 72h 02h 75h 73h ffh 76h 74h jedec sector map parameter dword-12 config-2 region-0 f2h bits 31:8 = 128mb device region size = 00feffh: region size as count-1 of 256 byte units = 255 x 64kb sectors = 16320kb count = 16320kb/256 = 65280, value = count -1 = 65280 -1 = 65279 = feffh bits 31:8 = 256mb device region size = 01feffh: region size as count-1 of 256 byte units = 511 x 64kb sectors = 32704kb count = 32704kb/256 = 130816, value = count -1 = 130816 -1 = 130815 = 1feffh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 64kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 64kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 64kb sector region 77h 75h ffh 78h 76h feh 79h 77h 00h (128mb) 01h (256mb) 7ah 78h jedec sector map parameter dword-13 config-2 region-1 f2h bits 31:8 = region size = 00007fh: region size as count-1 of 256 byte units = 1 x 32kb sectors = 32kb count = 32kb/256 = 128, value = count -1 = 128 -1 = 127 = 7fh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 32kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 32kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 32kb sector region 7bh 79h 7fh 7ch 7ah 00h 7dh 7bh 00h cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 2, sector map parameter table, 128mb and 256m b (sheet 3 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description
document number: 002-00368 rev. *j page 140 of 151 S25FS128S s25fs256s 7eh 7c jedec sector map parameter dword-14 config-2 region-2 f1h bits 31:8 = region size = 00007fh: region size as count-1 of 256 byte units = 8 x 4kb sectors = 32kb count = 32kb/256 = 128, value = count -1 = 128 -1 = 127 = 7fh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 4kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 4kb sector region bit 0 = erase type 1 support = 1b ---erase type 1 is 4kb erase and is supported in the 4kb sector region 7fh 7d 7fh 80h 7e 00h 81h 7f 00h 82h 80h jedec sector map parameter dword-15 config-1 header feh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 02h: three regions bits 15:8 = configuration id = 01h: 4kb sectors at bottom with remainder 256kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = not the end descriptor = 0 83h 81h 01h 84h 82h 02h 85h 83h ffh 86h 84h jedec sector map parameter dword-16 config-1 region-0 f1h bits 31:8 = region size = 00007fh: region size as count-1 of 256 byte units = 8 x 4kb sectors = 32kb count = 32kb/256 = 128, value = count -1 = 128 -1 = 127 = 7fh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b -- - erase type 3 is 256kb erase and is supported in the 4kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 4kb sector region bit 0 = erase type 1 support = 1b ---erase type 1 is 4kb erase and is supported in the 4kb sector region 87h 85h 7fh 88h 86h 00h 89h 87h 00h 8ah 88h jedec sector map parameter dword-17 config-1 region-1 f4h bits 31:8 = region size = 00037fh: region size as count-1 of 256 byte units = 1 x 224kb sectors = 224kb count = 224kb/256 = 896, value = count -1 = 896 -1 = 895 = 37fh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 1b ---erase type 3 is 256kb erase and is supported in the 32kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 32kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 32kb sector region 8bh 89h 7fh 8ch 8ah 03h 8dh 8bh 00h 8eh 8ch jedec sector map parameter dword-18 config-1 region-2 f4h bits 31:8 = 128mb device region size = 00fbffh: region size as count-1 of 256 byte units = 63 x 256kb sectors = 16128kb count = 16128kb/256 = 64512, value = count -1 = 64512 -1 = 64511 = fbffh bits 31:8 = 256mb device region size = 01fbffh: region size as count-1 of 256 byte units = 127 x 256kb sectors = 32512kb count = 32512kb/256 = 130048, value = count -1 = 130048 -1 = 130047 = 1fbffh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 1b ---erase type 3 is 256kb erase and is supported in the 64kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 64kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 64kb sector region 8fh 8dh ffh 90h 8eh fbh 91h 8f 00h (128mb) 01h (256mb) cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 2, sector map parameter table, 128mb and 256m b (sheet 4 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description
document number: 002-00368 rev. *j page 141 of 151 S25FS128S s25fs256s 92h 90h jedec sector map parameter dword-19 config-3 header feh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 02h: three regions bits 15:8 = configuration id = 03h: 4kb sectors at top with remainder 256kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = not the end descriptor = 0 93h 91h 03h 94h 92h 02h 95h 93h ffh 96h 94h jedec sector map parameter dword-20 config-3 region-0 f4h bits 31:8 = 128mb device region size = 00fbffh: region size as count-1 of 256 byte units = 63 x 256kb sectors = 16128kb count = 16128kb/256 = 64512, value = count -1 = 64512 -1 = 64511 = fbffh bits 31:8 = 256mb device region size = 01fbffh: region size as count-1 of 256 byte units = 127 x 256kb sectors = 32512kb count = 32512kb/256 = 130048, value = count -1 = 130048 -1 = 130047 = 1fbffh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 1b ---erase type 3 is 256kb erase and is supported in the 256kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 256kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 256kb sector region 97h 95h ffh 98h 96h fbh 99h 97h 00h (128mb) 01h (256mb) 9ah 98h jedec sector map parameter dword-21 config-3 region-1 f4h bits 31:8 = region size = 00037fh: region size as count-1 of 256 byte units = 1 x 224kb sectors = 224kb count = 224kb/256 = 896, value = count -1 = 896 -1 = 895 = 37fh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 1b ---erase type 3 is 256kb erase and is supported in the 224kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 224kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 224kb sector region 9bh 99h 7fh 9ch 9ah 03h 9dh 9bh 00h 9eh 9ch jedec sector map parameter dword-22 config-3 region-2 f1h bits 31:8 = region size = 00007fh: region size as count-1 of 256 byte units = 8 x 4kb sectors = 32kb count = 32kb/256 = 128, value = count -1 = 128 -1 = 127 = 7fh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 4kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 4kb sector region bit 0 = erase type 1 support = 1b ---erase type 1 is 4kb erase and is supported in the 4kb sector region 9fh 9dh 7fh a0h 9eh 00h a1h 9fh 00h a2h a0h jedec sector map parameter dword-23 config-4 header feh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 00h: one region bits 15:8 = configuration id = 04h: uniform 64kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = not the end descriptor = 0 a3h a1h 04h a4h a2h 00h a5h a3h ffh cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 2, sector map parameter table, 128mb and 256m b (sheet 5 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description
document number: 002-00368 rev. *j page 142 of 151 S25FS128S s25fs256s a6h a4h jedec sector map parameter dword-24 config-4 region-0 f2h bits 31:8 = 128mb device region size = 00ffffh: region size as count-1 of 256 byte units = 256 x 64kb sectors = 16mb count = 16mb/256 = 65536, value = count -1 = 65536 -1 = 65535 = ffffh bits 31:8 = 256mb device region size = 01ffffh: region size as count-1 of 256 byte units = 512 x 64kb sectors = 32mb count = 32mb/256 = 131072, value = count -1 = 131072 -1 = 131071 = 1ffffh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 64kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 64kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 64kb sector region a7h a5h ffh a8h a6h ffh a9h a7h 00h (128mb) 01h (256mb) aah a8h jedec sector map parameter dword-25 config-5 header ffh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 00h: one region bits 15:8 = configuration id = 05h: uniform 256kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = the end descriptor = 1 abh a9h 05h ach aah 00h adh abh ffh aeh ach jedec sector map parameter dword-26 config-5 region-0 f4h bits 31:8 = 128mb device region size = 00ffffh: region size as count-1 of 256 byte units = 64 x 256kb sectors = 16mb count = 16mb/256 = 65536, value = count -1 = 65536 -1 = 65535 = ffffh bits 31:8 = 256mb device region size = 01ffffh: region size as count-1 of 256 byte units = 128 x 256kb sectors = 32mb count = 32mb/256 = 131072, value = count -1 = 131072 -1 = 131071 = 1ffffh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 1b ---erase type 3 is 256kb erase and is supported in the 256kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 256kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 256kb sector region afh adh ffh b0h aeh ffh b1h afh 00h (128mb) 01h (256mb) cfi alternate vendor-specific extend ed query parameter a5h, jedec sfdp rev b, section 2, sector map parameter table, 128mb and 256m b (sheet 6 of 6) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description
document number: 002-00368 rev. *j page 143 of 151 S25FS128S s25fs256s 11.5 initial delivery state the device is shipped from cypress with non-volatile bits set as follows: ? the entire memory array is erased: i.e. all bits are set to 1 (each byte contains ffh). ? the otp address space has the first 16 bytes programmed to a random number. all other bytes are erased to ffh. ? the 33dp address space contains the values as defin ed in the description of the sfdp address space. ? the id-cfi address space contains the values as defi ned in the description of the id-cfi address space. ? the status register 1 non-volatile contains 00h (all sr1nv bits are cleared to 0?s). ? the configuration register 1 non-volatile contains 00h. ? the configuration register 2 non-volatile contains 08h. ? the configuration register 3 non-volatile contains 00h. ? the configuration register 4 non-volatile contains 10h. ? the password register contains ffffffff?ffffffffh. ? all ppb bits are 1. ? the asp register bits are ffffh.
document number: 002-00368 rev. *j page 144 of 151 S25FS128S s25fs256s ordering information 12. ordering part number the ordering part number is formed by a valid combination of the following: s25fs 256 s ag m f i 00 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 00 = soic16 / wson 6x8 mm footprint 10 = soic8 / wson 6x5 mm footprint 20 = 5x5 ball bga footprint 30 = 4x6 ball bga footprint 1d = soic8, ddr temperature range / grade i = industrial (?40c to + 85c) v = industrial plus (?40c to + 105c) a = automotive, aec-q100 grade 3 (-40c to +85c) b = automotive, aec-q100 grade 2 (-40c to +105c) m = automotive, aec-q100 grade 1 (-40c to +125c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 16-pin soic / 8-lead soic n = 8-contact wson 6 x 8 mm / wson 6 x 5 mm b = 24-ball bga 6 x 8 mm package, 1.00 mm pitch speed ag = 133 mhz sdr ds = 80 mhz ddr device technology s = 65 nm mirrorbit process technology density 128= 128 mbit 256= 256 mbit device family s25fs cypress memory 1.8 volt-only, serial peripheral interface (spi) flash memory
document number: 002-00368 rev. *j page 145 of 151 S25FS128S s25fs256s valid combinations ? standard valid combinations list configurations planne d to be supported in volume for this device. consult your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. S25FS128S, s25fs256s valid combinations ? standard valid combinations base ordering part number speed option package and temperature model number packing type package marking S25FS128S ag mfi, mfv 10 0, 1, 3 fs128s + (temp) + f + (model number) ag nfi, nfv 00, 10 0, 1, 3 fs128s + a + (temp) + f + (model number) ag bhi, bhv 20, 30 0, 3 fs128s + a + (temp) + h + (model number) ds mfi, mfv 1d 0, 1, 3 fs128s + (temp) + f + (model number) ds nfi, nfv 00, 10 0, 1, 3 fs128s + d + (temp) + f + (model number) ds bhi, bhv 20, 30 0, 3 fs128s + d + (temp) + h + (model number) s25fs256s ag mfi, mfv 00 0, 1, 3 fs256s + a + (temp) + f + (model number) ag nfi, nfv 00 0, 1, 3 fs256s + a + (temp) + f + (model number) ag bhi, bhv 20, 30 0, 3 fs256s + a + (temp) + h + (model number) ds mfi, mfv 00 0, 1, 3 fs256s + d + (temp) + f + (model number) ds nfi, nfv 00 0, 1, 3 fs256s + d + (temp) + f + (model number) ds bhi, bhv 20, 30 0, 3 fs256s + d + (temp) + h + (model number)
document number: 002-00368 rev. *j page 146 of 151 S25FS128S s25fs256s valid combinations ? au tomotive grade / aec-q100 the table below lists configurations that are automotive grade / aec-q100 qualified and are planned to be available in volume. the table will be updated as new combinations are released. consult your local sales representative to confirm availability of spec ific combinations and to check on newly released combinations. production part approval process (ppap) suppor t is only provided for aec-q100 grade products. products to be used in end-use applications that require iso/ts-16949 compliance must be aec-q100 grade products in combination with ppap. non?aec-q100 grade products are no t manufactured or documented in full compliance with iso/ts-16949 requirements. aec-q100 grade products are also offered without ppap suppor t for end-use applications that do not require iso/ts-16949 compliance. 13. contact obtain the latest list of company locations and contact information at www.cypress.com/contact-us . S25FS128S, s25fs256s valid combinations ? automotive grade / aec-q100 valid combinations base ordering part number speed option package and temperature model number packing type package marking S25FS128S ag mfa, mfb, mfm 10 0, 1, 3 fs128s + (temp) + f + (model number) ag nfa, nfb, nfm 00, 10 0, 1, 3 fs128s + a + (temp) + f + (model number) ag bha, bhb, bhm 20, 30 0, 3 fs128s + a + (temp) + h + (model number) ds mfa, mfb, mfm 1d 0, 1, 3 fs128s + (temp) + f + (model number) ds nfa, nfb, nfm 00, 10 0, 1, 3 fs128s + d + (temp) + f + (model number) ds bha, bhb, bhm 20, 30 0, 3 fs128s + d + (temp) + h + (model number) s25fs256s ag mfa, mfb, mfm 00 0, 1, 3 fs256s + a + (temp) + f + (model number) ag nfa, nfb, nfm 00 0, 1, 3 fs256s + a + (temp) + f + (model number) ag bha, bhb, bhm 20, 30 0, 3 fs256s + a + (temp) + h + (model number) ds mfa, mfb, mfm 00 0, 1, 3 fs256s + d + (temp) + f + (model number) ds nfa, nfb, nfm 00 0, 1, 3 fs256s + d + (temp) + f + (model number) ds bha, bhb, bhm 20, 30 0, 3 fs256s + d + (temp) + h + (model number)
document number: 002-00368 rev. *j page 147 of 151 S25FS128S s25fs256s 14. revision history document history page document title: S25FS128S/s25fs256s, 1.8 v, serial peripheral interface with multi-i/o, mirrorbit ? non-volatile flash document number: 002-00368 rev. ecn no. orig. of change submission date description of change ** ? ansi 04/05/2013 initial release *a ? ansi 04/08/2013 initial delivery state corrected information on configuration register 2 *b ? ansi 08/22/2013 global replaced ?quad all? with ?qpi? performance summary typical program and erase rates table: corrected kbytes / s migration notes spansion spi families comparison table: corrected page programming rate (typ.) for fs-s dc characteristics fs-s dc characteristics tabl e: added isb (automotive) sdr ac characteristics ac characteristics table: updated parameter for fsck, c registers latency code (cycles) versus frequency table: updated table added note 4 embedded algorithm performance tables program and erase performance table: corrected typ and max values for tpp ordering information added 1d and 5d to model number valid combinations table: corrected model number for S25FS128S *c ? ansi 11/06/2013 global changed data sheet designation from ?advance information? to ?preliminary? changed uson to wson physical interface added figure: 8-pin plastic small outline package (soic8) updated figure: 8-connector package (wson 6x5) removed figure: vsop thin 8-lead, 208 mil body width, (sov008) configuration register 4 updated output impedance control table ordering information updated model numbers and package type *d ? ansi 12/20/2013 migration notes changed quad read speed (ddr) for fl-s ddr ac characteristics updated ac characteristics 80 mhz operation table ddr output timing spi ddr data valid window figure: updated figure and notes
document number: 002-00368 rev. *j page 148 of 151 S25FS128S s25fs256s *e ? ansi 11/06/2014 global changed ?quad all? to ?qpi? changed ?sclk? to ?sck? performance summary typical current consumption (?40c to +85c) table: added deep power-down migration notes spansion spi families comparison table: added deep power-down updated deep power-down section interface states updated interface standby section data protection added deep power-down (dpd) section dc characteristics fs-s dc characteristics table: added idpd (industrial and automotive) updated active power and standby power modes section sdr ac characteristics ac characteristics table: added tdpd and tres ddr ac characteristics ac characteristics table: added tdpd and tres command set summary s25fs-s family command set (sorted by function) table: added dpd and res added dpd section reset commands added dpd commands section embedded algorithm performance tables corrected ?program and erase performance? table software interface reference s25fs-s family command set (sorted by instruction) table: added dpd and res *f 5043003 ansi 12/09/2015 updated to cypress template *g 5074674 pivi 02/02/2016 global changed status from preliminary to final. replaced ?automotive? with ?industrial plus? in all instances across the document. *h 5180929 gjsw 03/18/2016 updated ?software interface? on page 45 : updated ?commands? on page 76 : updated ?read memory array commands? on page 95 : updated ?quad i/o read (qior ebh or 4qior ech)? on page 99 : updated figure 9.34 (fixed bit values). updated figure 10.39 (fixed bit values). document history page (continued) document title: S25FS128S/s25fs256s, 1.8 v, serial peripheral interface with multi-i/o, mirrorbit ? non-volatile flash document number: 002-00368 rev. ecn no. orig. of change submission date description of change
document number: 002-00368 rev. *j page 149 of 151 S25FS128S s25fs256s *i 5445453 nfb 11/16/2016 added ecc related information in all instances across the document. updated program and erase cycles and retention to ?features? on page 1 . updated typical program and erase rates on page 2 . updated typical current consumption (?40c to +85c) on page 2 . added ?thermal resistance? on page 22 . added automotive grade to ?temperature ranges? on page 23 . updated fs-s dc characteristics on page 26 . updated ac characteristics on page 30 . added ?ecc status register (eccsr)? on page 63 . added ?ecc status register read (eccrd 19h or 4eecrd 18h)? on page 90 . updated ?read any register, qpi mode, command sequence? on page 94 . updated ?dual i/o read command sequence (bbh)? on page 98 . updated ?dual i/o continuous read command sequence (4-byte address [cr2v[7] = 1])? on page 99 . updated figures in ?quad i/o read (qior ebh or 4qior ech)? on page 99 . updated figures in ?ddr quad i/o read (edh, eeh)? on page 101 . added ?automatic ecc? on page 103 . updated ?embedded algorithm performance tables? on page 122 . updated program and erase performance on page 122 . updated program or erase suspend ac parameters on page 122 . added ?data integrity? on page 123 . removed software interface reference section. added ?valid combinations ? automotive grade / aec-q100? on page 146 . updated copyright and disclaimer. *j 5705491 ecao 04/21/2017 replaced v dd with v cc in all instances across the document. updated ?electrical specifications? on page 22 : updated ?operating ranges? on page 23 : updated ?temperature ranges? on page 23 : added ?automotive aec-q100 grade 1 (?40c to +125c)? temperature range related information. updated ?physical interface? on page 35 : updated ?soic 16-lead package? on page 35 : updated ?soic 16 physical diagram? on page 36 : updated figure 6.2 . updated ?8-connector packages? on page 37 : updated ?8-connector physical diagrams? on page 38 : updated figure 6.5 . updated figure 6.6 . updated figure 6.7 . updated ?fab024 24-ball bga package? on page 41 : updated ?physical diagram? on page 42 : updated figure 6.9 . updated ?fac024 24-ball bga package? on page 43 : updated ?physical diagram? on page 44 : updated figure 6.11 . document history page (continued) document title: S25FS128S/s25fs256s, 1.8 v, serial peripheral interface with multi-i/o, mirrorbit ? non-volatile flash document number: 002-00368 rev. ecn no. orig. of change submission date description of change
document number: 002-00368 rev. *j page 150 of 151 S25FS128S s25fs256s *j (cont.) 5705491 ecao 04/21/2017 updated ?ordering part number? on page 144 : added ?automotive aec-q100 grade 1 (?40c to +125c)? temperature range related information. updated ?valid combinations ? automotive grade / aec-q100? on page 146 : added ?automotive aec-q100 grade 1 (?40c to +125c)? temperature range related information. updated to new template. document history page (continued) document title: S25FS128S/s25fs256s, 1.8 v, serial peripheral interface with multi-i/o, mirrorbit ? non-volatile flash document number: 002-00368 rev. ecn no. orig. of change submission date description of change
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